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Altera MAX 10 series - Global Clock Gating; Hot Socketing; Hot-Socketing Specifications

Altera MAX 10 series
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Global Clock Gating
The dynamic power-down feature is available in GCLK networks only. You can use the power
management controller for the dynamic power-down of a GCLK network by controlling the active high
enout signal. The GCLK networks serve as low-skew clock sources for functional blocks such as logic
array blocks (LABs), DSP, embedded memory, and PLLs.
When a GCLK network is gated, all the logics fed by the GCLK network are in off-state. This reduces the
overall power consumption of the device. The dynamic power-down feature allows core logics to control
the following power-up and power-down conditions of the GCLK networks:
Power down synchronously or asynchronously
Power up asynchronously
Figure 2-6: GCLK Gating
Power
Management
Controller
enout
clk1
clkn gclkin
lenout
gclkout
Clock Control Block
Hot Socketing
The MAX 10 device offers hot socketing, which is also known as hot plug-in or hot swap, and power
sequencing support without the use of any external devices. You can insert or remove the MAX 10 device
on a board in a system during system operation. This does not affect the running system bus or the board
that is inserted into the system.
The hot-socketing feature removes some encountered difficulties when using the MAX 10 device on a
PCB that contains a mixture of devices with different voltage levels.
With the MAX 10 device hot-socketing feature, you no longer need to ensure a proper power-up sequence
for each device on the board. MAX 10 device hot-socketing feature provides:
Board or device insertion and removal without external components or board manipulation
Support for any power-up sequence
Non-intrusive I/O buffers to system buses during hot insertion
Hot-Socketing Specifications
The MAX 10 device is a hot-socketing compliant device that does not need any external components or
special design requirements. Hot-socketing support in the MAX 10 device has the following advantages:
UG-M10PWR
2015.11.02
Global Clock Gating
2-9
MAX 10 Power Management Features and Architecture
Altera Corporation
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