AMD XILINX VPK180 - Page 26

Figure 6: LPDDR4 Component Memory
XPIO
Triplet 1
XPIO
Triplet 2
XPIO
Triplet 3
700 701 702 703 704 705 706 707 708
LPDDR4
2x (1x32)
LPDDR4
2x (1x32)
LPDDR4
2x (1x32)
X26003-080522
XCVP1802 U1 has been congured with three triplet banks.
• XPIO triplet 1 (banks 700/701/702)
• XPIO triplet 2 (banks 703/704/705)
• XPIO triplet 3 (banks 706/707/708)
Each support two independent 32-bit 2 GB component interfaces (4 GB per triplet). The VPK180
evaluaon board uses the LPDDR4 memory components as follows:
• Manufacturer: Micron
• Part number: MT53D512M32D2DS-046 WT:D (dual die LPDDR4 SRAM)
• Component descripon
○ 16 Gb (512 Mb x 32)
○ 1.1V 200-ball WFBGA
○ DDR4-2133
The VPK180 XCVP1802 ACAP PL DDR interface performance is documented in the Versal
Premium Series Data Sheet: DC and AC Switching Characteriscs (DS959). The VPK180 evaluaon
board LPDDR4 component memory interfaces adhere to the constraints guidelines documented
in the PCB guidelines for the DDR4 secon of the Versal ACAP PCB Design User Guide (UG863).
The VPK180 DDR4 component interface is a 40Ω impedance implementaon. Other memory
interface details are also available in the Versal ACAP Memory Resources Architecture Manual
(AM007). For more memory component details, see the Micron MT53D512M32D2DS data
sheet at the Micron website. The detailed ACAP connecons for the feature described in this
secon are documented in the VPK180 evaluaon board XDC le, referenced in Appendix B:
Xilinx Design Constraints.
Chapter 3: Board Component Descriptions
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 26
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