AMD XILINX VPK180 - Page 27

System Reset POR_B
[Figure 4, callout 2]
POR_B is the Versal ACAP processor reset, which can be controlled by:
• SYSCTLR (U125)
• PC4 header (J36)
• FTDI USB JTAG chip (U20)
In the following gure, U235 allows direconal open drain level shiing for all of these masters,
and J326 allows them to be bused together if desired. The TPS389001 U10 supervisor chip
holds POR_B o unl power is valid. The VPK180 board POR circuit is shown in the following
gure.
Chapter 3: Board Component Descriptions
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 27
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