AMD XILINX VPK180 - Page 37

Informaon for the SD I/O card specicaon can be found at the SanDisk Corporaon or SD
Associaon websites. The VPK180 SD card interface supports the SD1 (2.0) and SD2 (3.0)
conguraon boot modes documented in the Versal ACAP Technical Reference Manual (AM011).
See schemac page 51 for more details.
For NVP NVT4857UK component details, see the NVT4857UK data sheet on the NXP website.
The detailed ACAP connecons for the feature described in this secon are documented in the
VPK180 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
PS MIO[37] Reserved
The ACAP PS bank 501 MIO37 is factory reserved.
PMC MIO[39:41] System Monitor I2C
The ACAP PS bank 501 MIO39 (PMC_MIO39_SYSMON_I2C_SCL), MIO40
(PMC_MIO40_SYSMON_I2C_SDA), and MIO41 (PMC_MIO41_SYSMON_I2C_ALERT) are
connected to the system controller for use with the system controller related applicaons and
alerts.
PMC MIO[42:43] UART0
[Figure 3, callout 9]
This is the primary Versal ACAP PS-side UART interface. MIO42 (RX_IN) and MIO43 (TX_OUT)
are connected to FTDI FT4232HL U20 USB-to-Quad-UART bridge port BD through TI
SN74AVC4T245 level-shiers U18 and U271. The FT4232HL U20 port assignments are listed in
the following table.
Table 9: FT4232HL Port Assignments
FT4232HL U34 Versal ACAP U1
Port AD JTAG VPK180 JTAG chain
Port BD UART0 PS_UART0 (MIO 42-43)
Port CD UART1 PL_UART1 bank 712
Port DD UART2 U20 system controller UART
The FT4232HL UART interface connecons are shown in the following gure.
Chapter 3: Board Component Descriptions
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 37
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