AMD XILINX VPK180 - Page 47

See the "FT4232HL UART Connecons" gure in PMC MIO[42:43] UART0 for an overview of
FT4232 U20 JTAG and USB-UART connecvity.
Clock Generation
The VPK180 board provides xed and variable clock sources for the XCVC1802 U1 ACAP and
other funcon blocks. The following table lists the source devices for each clock.
Table 16: Clock Sources
Ref. Des. Feature Notes
Schematic
Page
U248 DDR4 DIMM CLK, 200 MHz, 3.3V LVDS, 0x60 Skyworks/Silicon Labs
570BAB000299DG
3
U3 DDR4 DIMM CLK, 200 MHz, 3.3V LVDS, 0x60 Skyworks/Silicon Labs
570BAB000299DG
4
U4 DDR4 DIMM CLK, 200 MHz, 3.3V LVDS, 0x60 Skyworks/Silicon Labs
570BAB000299DG
5
U312 HSDP System Controller REFCLK1, 156.25 MHz,
3.3V LVDS
CTS 626L15625I3T 8
U313 HSDP System Controller REFCLK1, 156.25 MHz,
3.3V LVDS
CTS 626L15625I3T 8
U32 ACAP U1 REF CLK, 33.33 MHz, 1.8V CMOS, 0x5D Skyworks/Silicon Labs
570JAC000900DGR
54
U298 ACAP U1 GTM CLK, 156.25 MHz, 1.8V LVDS, 0x09 Renesas RC21008A065GND 61
U299 ACAP U1 GTM CLK, 156.25 MHz, 1.8V LVDS, 0x09 Renesas RC21008A065GND 62
U219 IEEE-1588 eCPRI CLK, various, 3.3V, 0x5B Renesas/IDT 8A34001E-000AJG8 90
The detailed ACAP connecons for the feature described in this secon are documented in the
VPK180 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
Programmable LPDDR4 SI570 Clock
[Figure 3, callout 38, 39, 40]
The VPK180 evaluaon board has I2C programmable SI570 low-jier 3.3V LVDS dierenal
oscillators (U248, U3, U4) connected to the GC inputs of U1 DDR4 DIMM interface bank 702,
705, and 708, respecvely. The LPDDR4_CLK1_P/N, LPDDR4_CLK2_P/N and
LPDDR4_CLK3_P/N series capacitor coupled clock signals are connected to XCVP1802 ACAP
U1. At power-up, this clock defaults to an output frequency of 200.000 MHz. User applicaons
or the system controller can change the output frequency within the range of 10 MHz to 945
MHz through the I2C bus interface. Power cycling the VPK180 evaluaon board reverts this user
clock to the default frequency of 200.000 MHz.
• Programmable oscillator: Skyworks/Silicon Labs SI570BAB000299DG
• 10 MHz-945 MHz range, 200.000 MHz default
Chapter 3: Board Component Descriptions
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 47
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