AMD XILINX VPK180 - Page 63

Note: The integrated HSDP Aurora interface is not available in all Versal ACAPs, which might support
HSDP using a so Aurora soluon. This interface requires addional conguraon in the Control,
Interfaces, and Processing (CIPS) IP, a PL aurora implementaon, and the use of addional gigabit
transceivers.
User I/O
[Figure 4, callout 14, 15 and Figure 3, callout 44]
See Switches for default values.
The following table lists the net names, reference designators, and schemac pages for the user
I/O.
Table 19: User I/O
Net Name Ref. Designator Schematic Pages
GPIO_PB0 SW4 6/65
GPIO_PB1 SW5 6/65
GPIO_DIP_SW0 SW6 7/65
GPIO_DIP_SW1 SW6 7/65
GPIO_DIP_SW2 SW6 7/65
GPIO_DIP_SW3 SW6 7/65
GPIO_LED_0_LS DS6 7/65
GPIO_LED_1_LS DS5 7/65
GPIO_LED_2_LS DS4 7/65
GPIO_LED_3_LS DS3 7/65
Power and Status LEDs
[Figure 3, callout 30]
The following gure shows the power and status LEDs.
Chapter 3: Board Component Descriptions
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 63
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