AMD XILINX VPK180 - Page 9

○ User SMA connectors (1, bank GTM219)
○ 8A34001 CLK (1, bank GTM219)
• PS PMC MIO connecvity
○ PS MIO[0:12]: boot conguraon QSPI
- DC QSPI support
○ PS MIO[13:25]: USB2.0
○
PS MIO[26:36, 51]: SD1 I/F
○ PS MIO[37]: ZU4_TRIGGER
○ PS MIO[38]: Not connected
○ PS MIO[39:41]: SYSMON_I2C
○ PS MIO[42:43]: UART0 to FTDI
○ PS MIO[44:47]: I2C1, I2C0
○ PS MIO[48], PS LPD MIO[0:11, 24:25]: GEM0 RGMII Ethernet RJ-45
○ PS MIO[49] and LPD MIO[13,15:16,20]: power enable
○ PS MIO[50] and LPD MIO[18:19]: Not connected
○ PS LPD MIO [21:22]: oponal fan interface
○ LPD MIO[23]: VADJ_FMC power rail
• Security: PSBATT buon baery backup
• SYSMON header
• Operaonal switches (power on/o, PROG_B, boot mode DIP switch)
• Operaonal status LEDs (INIT, DONE, PS STATUS, PGOOD)
○ See Power and Status LEDs
• Power management
• System controller (XCZU4EG)
The VPK180 evaluaon board provides a rapid prototyping plaorm using the
XCVP1802-2MSELSVC4072 device. See the Versal Architecture and Product Data Sheet: Overview
(DS950) for a feature set overview, descripon, and ordering informaon.
Chapter 1: Introduction
UG1582 (v1.0) February 21, 2023 www.xilinx.com
VPK180 Board User Guide 9
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