AMD Xilinx ZCU670 - Page 24

Figure 6: Encryption Key Battery Backup Circuit
X25697-090221
The Seiko TS621E rechargeable 1.5V lithium buon-type baery B1 is soldered to the board
with the posive output connected to the ZU67DR RFSoC U1 VCC_PSBATT pin AE29. The
baery supply current IBATT specicaon is 150 nA maximum when board power is o. B1 is
charged from the VCC1V8 1.8V rail through a series diode with a typical forward voltage drop of
0.38V and 4.7 ΩK current limit resistor. The nominal charging voltage is 1.42V.
I/O Voltage Rails
The ZU67DR RFSoC PL I/O bank voltages on the ZCU670 board are listed in the following table.
Table 6: I/O Voltage Rails
ZU67DR
Power Net
Name
Voltage Connected To
PL Bank 65 VCC1V2 1.2V PL_DDR4_C0_DQx, MSP430_UCA1, UART2
PL Bank 66 VCC1V2 1.2V PL_DDR4_C0_Ax, USER_SI570_C0, SI5381_PL_CLK,
ADCIO[08:15], DACIO[08:15]
PL Bank 67 VCC1V8 1.8V ADCIO[00:07], DACIO[0:07], SI5381_CLK2_IN,
8A34001_Q3_OUT, SI5381_CLK_125,
CLK104_CLK_SPI_MUX_SEL[0:1]
PL Bank 88 VCC1V8 1.8V SYSMON_SDA/SCL, CPU_RESET, GPIO_SW_PL,
SI5381_CLK104_MUX_SEL, SI53340_MUX_GT_SEL,
SI53340_MUX_GTR_SEL, CLK104_PL_CLK,
8A34001_Q2_OUT, MUX_PL_SYSREF,
8A34001_CLK6_IN, GPIO_LED[0:3],
MSP430_GPIO[0:3]
PS Bank 500
VCC1V8 1.8V MIO_LED/PB, UART0, MIO_I2C0/1, PS_GPIO2, QSPI
LWR/UPR
PS Bank 501 VCC1V8 1.8V SDIO I/F, PMU_GPO[0:5], SFP[0:3]_TX_DISABLE,
PMU_INPUT
PS Bank 502 VCC1V8 1.8V ENET I/F, USB (3.0) I/F
PS Bank 503 VCC1V8 1.8V PS CONFIG I/F, JTAG I/F
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 24
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