AMD Xilinx ZCU670 - Page 23

Figure 5: Zynq UltraScale+ RFSoC DFE Block Diagram
Complex
equalizer
Mixer
& DDC
eCPRI framing/de-framing
O-RAN interface
O-RAN user/control plane
iFFT
DUC &
mixer
CFR
DPD
P/Q re-
sampler
Clocking
25GE MAC PCS/PMA & RSFEC
Prog.
channel
filter
Prog.
channel
filter
FFT
PRACH
filter &
FFT
P/Q re-
sampler
P/Q re-
sampler
Adaptable Logic Fabric
· ORAN/CPRI/eCPRI logic
· Non-supported use cases
· FD & TD buffers, gain control
· CP insertion/removal, windowing
· DPD update, TX equalizer, TX/RX AGC
· Timing & synchronization
· Power meters, data capture/insertion
· Signal statistics, debug
Calibration diagnostics
Processor Subsystem
System configuration
DPD update
DFE
DAC
DFE
ADC
DFE
ADC
DFE IP
Prog. Logic
Processor
X25919-102921
For more informaon on the Zynq UltraScale+ RFSoC DFE, see the Breakthrough Adapve Radio
Plaorm website and the Zynq UltraScale+ RFSoC DFE Data Sheet: Overview (DS883).
Encryption Key Battery Backup Circuit
The Zynq UltraScale+ RFSoC ZU67DR U1 implements bit stream encrypon key technology. The
ZCU670 board provides the encrypon key backup baery circuit shown in the gure below.
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 23
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