AMD Xilinx ZCU670 - Page 22

The Zynq UltraScale+ RFSoC PS block has three major processing units:
• Cortex-A53 applicaon processing unit (APU) Arm v8 architecture-based 64-bit quad-core
mulprocessing CPU.
• Cortex-R5F real-me processing unit (RPU) Arm v7 architecture-based 32-bit dual RPU with
dedicated ghtly-coupled memory (TCM).
• Mali-400 graphics processing unit (GPU) with pixel and geometry processor and 64 KB L2
cache.
The Zynq UltraScale+ RFSoC PS has four high-speed serial I/O (HSSIO) interfaces supporng the
following protocols:
• Integrated block for PCI Express
®
interface-PCIe base specicaon version 2.1 compliant.
• SATA 3.1 specicaon compliant interface.
• USB 3.0 interface-compliant to USB 3.0 specicaon implemenng a 5 Gb/s line rate.
• Serial GMII interface-supports a 1 Gb/s SGMII interface.
The PS and PL can be coupled with mulple interfaces and other signals to eecvely integrate
user-created hardware accelerators and other funcons in the PL logic that are accessible to the
processors. They can also access memory resources in the processing system. The PS I/O
peripherals, including the stac/ash memory interfaces share a mulplexed I/O (MIO) of up to
78 MIO pins. Zynq UltraScale+ RFSoCs can also use the I/O in the PL domain for many of the PS
I/O peripherals. This is done through an extended mulplexed I/O interface (EMIO) and boots at
power-up or reset.
The ZCU670 is an evaluaon board featuring the ZU67DR Zynq UltraScale+ RFSoC DFE device.
This board enables the evaluaon of applicaons requiring mul-band (sub-7 GHz, mmWave),
mul-std (5G, LTE, etc.), and mul-mode (TDD, FDD) radios, including Milcom and Satcom
applicaons. The ZCU670 board is equipped with all the common board-level features needed
for design development, such as DDR4 memory, networking interfaces, an FMC+ expansion port,
as well as access to the RFMC 2.0 interface.
The ZU67DR includes not only the direct RF sampling converters but also a fully dedicated
digital front-end (DFE) subsystem with all the required signal processing blocks. With this
dedicated IP, the ZCU670 enables ~50% lower power (at 500 MHz) versus equivalent so IP
implementaon. The DFE blocks implement the key wireless DFE logic in dedicated blocks and
has mulple instances placed within the programmable logic fabric. Each dedicated IP block can
be bypassed and appended for maximum exibility and customizaon.
The following gure shows the Zynq UltraScale+ RFSoC DFE block diagram.
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 22
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