AMD Xilinx ZCU670 - Page 43

Table 17: ZCU670 Board Clock Sources (cont'd)
Clock (Net) Name Frequency Clock Source
Programmable Frequency Clocks
USER_SI570_C0 300 MHz (Default) U47 SI570 I2C PROG. OSC. (0x5D)
USER_MGT_SI570_CLOCK 156.25 MHz (Default) U48 SI570 I2C PROG. OSC. (0x5D)
BUF_GTR_REF_CLK0 – U429 SI53340 clock multiplexer
BUF_GTR_REF_CLK1 –
BUF_GTR_REF_CLK3 –
SI5381_DAC_REFCLK 122.88 MHz (Default) U43 SI5381A PROG. CLK GEN (0x76)
SI5381_AMS_SYSREF –
SI5381_PL_SYSREF –
SI5381_ADC_REFCLK 122.88 MHz (Default)
SI5381_PL_CLK 245.76 MHz (Default)
SI5381_SMA_SE 10 MHz (Default)
ADC_CLK_226 User-provided source J8 (P)/J98 (N) SSMP connector
DAC_CLK_228 User-provided source J99 (P)/J100 (N) SSMP connector
Various 8A34001 eCPRI clocks Various U409 8A34001 (0x58)
The following table lists the connecons for each clock.
Table 18: Clock Connections to ZU67DR U1
Clock Source Ref. Des. and
Pin
Net Name I/O Standard
U130 SI570 I2C PROG. OSC.
U130.4 PS_REF_CLK (series R300) 1
U47 SI570 I2C Prog. Oscillator DDR4 C0 I/F (300 MHz Default)
U47.4 USER_SI570_C0_P LVDS
U47.5 USER_SI570_C0_N LVDS
U48 SI570 I2C PROG. OSC. (156.25 MHz Default)
U48.4 USER_MGT_SI570_CLOCK_P 2
U48.5 USER_MGT_SI570_CLOCK_N 2
U43 SI5381A Programmable Clock Generator
U43.21 SI5381_DAC_REFCLK_P 2
U43.20 SI5381_DAC_REFCLK_N 2
U43.24 SI5381_AMS_SYSREF_P LVDS
U43.23 SI5381_AMS_SYSREF_N LVDS
U43.28 SI5381_PL_SYSREF_P LVDS
U43.27 SI5381_PL_SYSREF_N LVDS
U43.35 SI5381_ADC_REFCLK_P 2
U43.34 SI5381_ADC_REFCLK_N 2
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 43
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