AMD Xilinx ZCU670 - Page 42

Figure 16: JTAG Chain Block Diagram
JTAG
2 mm 2X7
Header
J25
TDO
TDI
FT4232HL
UART
BRIDGE
U29
TDO
TDI
JTAG
IF
PS Config
Bank 503
U1
TDI
TDO
JTAG
TDI
BUF
U27
A B
U42
JTAG
TDO
BUF
U25
B A
FMCP HSPC
Connector
J28 (D)
TDI TDO
N.C.
X23652-012220
Clock Generation
The ZCU670 board provides xed and variable clock sources for the ZU67DR Zynq UltraScale+
RFSoC. The following table lists the source devices for each clock.
Table 17: ZCU670 Board Clock Sources
Clock (Net) Name Frequency Clock Source
Fixed Frequency Clocks
PS_REF_CLK 33.33 MHz U130 SI570 I2C PROG. OSC. (0x5D)
SI5381_CLK_125 125 MHz U43 SI5381A PROG. CLK GEN (0x76)
SI5381_GTR_REFCLK_USB3 26 MHz
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 42
Send Feedback