AMD Xilinx ZCU670 - Page 41

Table 16: Ethernet PHY LED Functional Description (cont'd)
Pin Name Type Description
LED_0 S, I/O, PD
By default, this pin indicates that link is established.
Additional functionality is configurable by means of LEDCR1[3:0] register bits.
The LED funcons can be re-purposed with a LEDCR1 register write available through the PHYs
management data interface, MDIO/MDC. LED_2 is assigned to ACT (acvity indicator) and
LED_0 indicates link established.
LED_1 (100BASE-T link established) is a separate LED DS8 located on the top side of the board
near the RJ45 P1 connector (Figure 2, callout 16).
For more Ethernet PHY details, see the TI DS83867 data sheet on the Texas Instruments
website.
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU670 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
Programmable Logic JTAG Programming Options
[Figure 2, callouts 8 and 9]
ZCU670 JTAG chain:
• J24 USB micro AB connector connected to U29 FT4232HL USB-JTAG bridge
• J25 2x7 2 mm shrouded, keyed JTAG pod at cable connector
The ZCU670 board JTAG chain is shown in the following gure.
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 41
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