AMD Xilinx ZCU670 - Page 40

10/100/1000 MHz Tri-Speed Ethernet PHY
[Figure 2, callout 16]
The ZCU670 board uses the TI DP83867IRPAP Ethernet RGMII PHY (U33) (see Texas
Instruments website) for Ethernet communicaons at 10 Mb/s, 100 Mb/s, or 1000 Mb/s. The
board supports RGMII mode only. The PHY connecon to a user-provided Ethernet cable is
through a Wurth 7499111221A RJ-45 connector (P1) with built-in magnecs.
Ethernet PHY Reset
The DP83867IRPAP PHY U33 reset circuit is shown in the following gure. The DP83867IRPAP
can be reset by the GEN3_EXP_RESET_B signal through the I2C0 TCA6416A U15 bus expander
P06 pin 10 or the PS_POR_B signal generated by the MAX16025 U6 POR device pin 11.
SW4 pushbuon at the MAX16025 U5 pin 6 input also triggers a PS_POR_B signal.
Figure 15: Ethernet PHY Reset Circuit
X25883-101921
Ethernet PHY LED Interface
[Figure 2, callout 16]
The DP83867IRPAP PHY U33 LED interface (LED_0, LED_2) uses the two LEDs embedded in
the P1 RJ45 connector bezel. The LED funconal descripon is as shown in the following table.
Table 16: Ethernet PHY LED Functional Description
Pin Name Type Description
LED_2 S, I/O, PD
By default, this pin indicates receive or transmit activity.
Additional functionality is configurable by means of LEDCR1[11:8] register bits.
Note: This pin is a strap configuration pin for RGZ devices only.
LED_1 S, I/O, PD
By default, this pin indicates that 100BASE-T link is established.
Additional functionality is configurable by means of LEDCR1[7:4] register bits.
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 40
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