AMD Xilinx ZCU670 - Page 55

See the FPGA Mezzanine Card (FMC) VITA 57.4 specicaon on the VITA FMC Markeng
Alliance website for addional informaon on the FMCP HSPC connector.
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU670 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
Cooling Fan Connector
[Figure 2, near callout 33]
The ZCU670 uses the Inneon MAX6643 (U50) fan controller, which autonomously controls the
fan speed by controlling the pulse width modulaon (PWM) signal to the fan based on the die
temperature sensed via the FPGA's DXP and DXN pins. The fan rotates slowly (acouscally quiet)
when the RFSoC is cool and rotates faster as the FPGA heats up (acouscally noisy). The fan
speed (PWM) versus the RFSoC die temperature algorithm along with the over temperature set
point and fan failure alarm mechanisms are dened by the strapping resistors on the MAX6643
device. The over temperature and fan failures alarms can be monitored by any available
processor in the RFSoC by polling the I2C expander U15 on the I2C0 bus. See the MAX6643
data sheet on the Maxim Integrated Circuits website for more informaon on the device circuit
implementaon on this board.
The ZCU670 cooling fan circuit is shown in the following gure.
Note: At inial power on, it is normal for the fan controller to energize at full speed for a few seconds.
Figure 19: ZCU670 Cooling Fan Circuit
X25884-101921
VADJ_FMC Power Rail
The ZCU670 evaluaon board implements the ANSI/VITA 57.1 secon 5.5.1 IPMI support
funconality. The power control of the VADJ_FMC power rail is managed by the U38 system
controller. This rail powers the FMCP HSPC (J28) VADJ pins, as well as the ZU67DR HP banks 66
and 67. The valid values of the VADJ_FMC rail are 1.2V, 1.5V, and 1.8V.
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 55
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