AMD Xilinx ZCU670 - Page 54

Bank 505 lanes 0, 1, and 3 support FMC+ over J28.
Bank 505 reference clocks are connected to the U43 SI5341A clock generator as described in
SI5381A 10 Independent Output Any-Frequency Clock Generator U43.
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU670 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
FPGA Mezzanine Card Interface
The ZCU670 evaluaon board supports the VITA 57.4 FPGA mezzanine card plus (FMC+ or
FMCP) specicaon by providing a subset implementaon of the high pin count connector at J28
(HSPC). FMC+ connectors use a 14 x 40 form factor, populated with 560 pins. The connector is
keyed so that a mezzanine card, when installed on the ZCU670 evaluaon board, faces away
from the board.
FMCP Connector J28
Samtec SEAF series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector. More
informaon about SEAF series connectors is available on the Samtec, Inc. website. More
informaon about the VITA 57.4 FMC+ specicaon is available on the VITA FMC Markeng
Alliance website.
The 560-pin FMC+ connector dened by the FMC specicaon (see Appendix A: VITA57.4
FMCP Connector Pinout) provides connecvity for up to:
• 160 single-ended or 80 dierenal user-dened signals
• 24 transceiver dierenal pairs
• 6 transceiver dierenal clocks
• 4 dierenal clocks
• 239 ground and 19 power connecons
FMCP Connector J28
[Figure 2, callout 25]
The HSPC connector J28 implements a subset of the full FMCP connecvity:
• 68 single-ended or 34 dierenal user-dened pairs (34 LA pairs: LA[00:33])
• 8 transceiver dierenal pairs
• 2 transceiver dierenal clocks
• 2 dierenal clocks
• 239 ground and 16 power connecons
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 54
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