AMD Xilinx ZCU670 - Page 53

GTY Transceivers
The GTY transceivers in the ZU67DR are grouped into two channels or quads. The reference
clock for a quad can be sourced from the quad above or the quad below the GTY quad of
interest. The two GTY quads used on the ZCU670 board have the connecvity listed below. The
following table shows the MGTY assignments.
Table 21: ZCU670 ZU67DR GTY Mapping
ZCU670 ZU67DR-FSVE1156 GTY Mapping
ZU67DR-FSVE1156
SFP3
ch3
GTY Quad 127
SFP2
ch2
SFP1 ch1
SFP0 ch0
USER_MGT_REFCLK refclk1
8A34001_CLK1 refclk0
FMCP_HSPC_DP3 ch3
GTY Quad 128
FMCP_HSPC_DP2
ch2
FMCP_HSPC_DP1 ch1
FMCP_HSPC_DP0 ch0
8A34001_Q11_OUT refclk1
8A34001_CLK2_IN refclk0
zSFP+
Four MGTs are provided by PL-side MGT banks 127 and 128 for the quad (2x2 connector) zSFP+
interface. Available GTY reference clocks include two sets of clocks to/from IDT 8A34001 U409.
Each zSFP+ connector provides an I2C based control interface. This I2C interface is accessible for
each individual zSFP+ module through the I2C mulplexer topology on the ZCU670.
For addional informaon on GTY transceivers, see the UltraScale Architecture GTY Transceivers
User Guide (UG578).
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU670 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
PS GTR Transceivers
The PS-side GTR transceiver Bank 505 supports USB (3.0). The remainder of the GTR
transceivers are connected to the FMC+ connector.
Bank 505 USB0 lane 2 supports the USB0 (USB3.0) interface described in USB 3.0 Transceiver
and USB 2.0 ULPI PHY. The PS-side GTR transceiver provides USB 3.0 host-only connecvity.
See Appendix A: VITA57.4 FMCP Connector Pinout.
Chapter 3: Board Component Descriptions
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 53
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