AMD Xilinx ZCU670 - Page 7

• PS GTR (bank 505) assignment
○ USB3 (1 GTR)
○ FMCP HSPC DP (3 GTR)
• PL GTY assignment (2 quads, 8 total GTY)
○ 2x2 zSFP+ (4 GTY on bank GTY127)
○ FMCP HSPC DP (4 GTY, bank GTY128)
• PS MIO connecvity
○ PS MIO[0:5, 7:12]: dual QSPI
○ PS MIO[13]: PS_GPIO2
○ PS MIO[14:17]: 2 channels of I2C
○ PS MIO[18:19]: UART0 (1 of 3 FT4232 UART channels)
○ PS MIO[22:23]: PS_PB, PS_LED I/F
○ PS MIO[26]: PMU_INPUT
○ PS MIO[27:30]: SFP[0:3] TX_DISABLE
○ PS MIO[32:37]: PMU_GPO[0:5]
○ PS MIO[38]: PS_GPIO1
○ PS MIO[39:43, 45:51]: SD I/F
○ PS MIO[52:63]: USB3.0
○ PS MIO[64:77]: Ethernet RGMII
• PL I/O connecons
○ PL user GPIO pushbuon
○ PL CPU reset pushbuon
○ PL user GPIO LEDs (4)
• Security—PSBATT buon baery backup
• SYSMON header
• Operaonal switches (power on/o, PS_PROG_B, boot mode DIP switch)
• Operaonal status LEDs (INIT, DONE, PS STATUS, PGOOD)
• Power management
• System controller (MSP430)
Chapter 1: Introduction
UG1532 (v1.0) March 30, 2022 www.xilinx.com
ZCU670 Board User Guide 7
Send Feedback