Amiga 1000 - Page 31

BASIC
OPERATING
THEORY
'OMMODORE-
AMIGA
1000 SYSTEM
SLIDE
10
—
SPRITE
DMA
There are
8 Sprite
Controllers.
Each is
independent and uses 1
DMA Channel,
(3
Total),
and has its
own
dedicated
time
slot for DMA Data
Transfer.
Sprites
are
Line
Buffered
Objects
that can move very fast
because positioning
is controlled
by
Hardware
Registers
and Comparators.
Each
Sprite has
two 16 3it Data
Registers which define
a Sprite
16 Pixels wide
with
4
Colors. Each
Sprite also
has
a
Horizontal
Position
Register, Vertical
Position Register,
Vertical Start
Position
Register and
Vertical
Stop Position
Register
whic
allows Variable
Vertical Size
Sprites.
The Sprite DMA
Controller
fetches
Image Data and
Position
Data automatically
from anywhere
in the
512K
of memory.
Sorites can be run
automatically
in DMA Mode
or loaded
and
controlled
>
by the
68000 MPU.
Each
Sprite
can
be re-used
Vertically as
often
as desired
but
Horizontal
re-use
is
possible only
under control of the
68000
MPU.
SLIDE
11
—
PAULA
BLOCK
The
8364 PAULA is
the Ports,
Audio and Uart Chip. Its
main
function, in chip
area, is the
4
Audio
Channels.
It
also contains the I/O
Ports, (Disk and
Pots),
Serial Port,
(Uart)
, and the Interrupt Control
and Status
Structure.
The
4
Audio
Channels
each
have
a DMA
Pointer Register, Data Register, Period,
(Frequency)
, Register
and
Volume Register. Each Channel
has an on chip
D to
A,
(Digital
to
Analog) ,
Converter on
the output. The 4 Channels are grouped
into
a
Right and a
Left
Audio Output.
The Disk
Controller has
Registers for
Data
Read, Data Write
and
Control. It
also
contains
a
Preccmpensation
Output Circuit
a
Data
Separator
Input
Circuit
with
a Digital
Phase Lock Loop.
The Serial
Port UART
included on PAULA
contains
Data
Registers,
Control
Registers
and Transmit, (TON)
,
and
Receive, (REC)
,
Registers.
The
4 Pot Ports
are
General Purpose I/O
Ports.
They
have
Counters
for
simple A
to D,
(Analog
to
Digital),
Conversion
of
External
Capacitor
Charging
which could
be
used
for Analog
Joystick
Controllers.
The Audio,
Disk and
UART
controllers
all
set their
own
Interrupt
Status
Register
Bits. The
Audio
and Disk
Controllers
also
go to
the
DMA
Request
Logic,
(Remember: They
are
DMA Users) ,
causing the
DMAL
Signal to
request
DMA Cycles
from
AGNUS.
SLIDE 12
—
DISK
DMA
The
Disk
Controller uses
only 1 DMA
Channel
with its
own
dedicated
time
slots
for
Data Transfer.
A
Block of
Memory, up to
128K
in
length, can
be
read
from
or
written to
anywhere
in the
512K of
memory.
It has
Adjustable Pre-ccmpensation
for
writing
disks,
Digital
PLL,
(Phase
Locked
Loop)
,
for
reading disks
and a
Dual
Speed
Data Rate
to
allow
most
corrmom
FM,
MFM,
and
GCR
Formats
to be utilized.
)