Chapter 3 Hardware
26 Reference Manual CoreModule 420
Pin # Signal Description (P1 Row D)
31 (D10) DAck5*
DMA Acknowledge 5 – Used by DMA controller to select the I/O
resource requesting the bus, or to request ownership of the bus as a bus
master device. Can also be used by the ISA bus master to gain control of
the bus from the DMA controller.
32 (D11) DRQ5
DMA Request 5 – Used by I/O resources to request DMA service. Must
be held high until associated DACK5 line is active.
33 (D12) DAck6*
DMA Acknowledge 6 – Used by DMA controller to select the I/O
resource requesting the bus, or to request ownership of the bus as a bus
master device. Can also be used by the ISA bus master to gain control of
the bus from the DMA controller.
34 (D13) DRQ6
DMA Request 6 – Used by I/O resources to request DMA service. Must
be held high until associated DACK6 line is active.
35 (D14) DAck7*
DMA Acknowledge 7 – Used by DMA controller to select the I/O
resource requesting the bus, or to request ownership of the bus as a bus
master device. Can also be used by the ISA bus master to gain control of
the bus from the DMA controller.
36 (D15) DRQ7
DMA Request 7 – Used by I/O resources to request DMA service. Must
be held high until associated DACK7 line is active.
37 (D16) +5V +5V Power +/- 10%
38 (D17) Master* Bus Master Assert – This signal is used by an ISA board along with a
DRQ line to gain ownership of the ISA bus. Upon receiving a -DACK a
device can pull -MASTER low which will allow it to control the system
address, data, and control lines. After -MASTER is low, the device
should wait one CLK period before driving the address and data lines,
and two clock periods before issuing a read or write command.
39 (D18) GND Ground
40 (D19) GND Ground
Notes: The shaded area denotes power or ground. The signals marked with * indicate active low.
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