Anadex DP-9000 - Serial Interface Signal Timing Relationships

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DATA

FLOW

<~

l..

r

I = BAUD RATE BUFFER FULL

CONDITION

I

I- I- I-

I

l-

I

~

II

121314151617181

SliP

I

~

II

121314151617181

SliP

I

~

II

121314151617181

SliP

I

~II

121314151617181

S'IP

1

j.-

DATA

----I

p I

PRINTER

INITIALIZATION

(2)

1

~II

121314151617181

SIr

1

I I I I

I :

~

14--2

m.

sec. Max.

I,

I,

I

SPACE

(0)1

I

DATA

IN

,

MARK (

I)

...,

----------

SPACE

(0)

STX H 1 ETX

DATA

OUT

MARK

(1)1

11---';"'"

I

ACK

I

CTS

--+

\ UNSTRAPPED I

I

I~

RTS

.-1

sJ

I

I

I

SRTS+-

~

I~f----------------

, I

I I

: '

DTR

.-

J I t J

I I

I I

I

I'

DSR

--

\ UNSTRAPPED

I~

\ f S I

TO

ILLUSTRATE SRTS

ACTION ONLY.

NO

TIMING RELATIONSHIP

TO

CTS,RTS

OR

ACK.

N

I

N

t---l

FIGURE

2-9.

SERIAL

INTERFACE

SIGNAL

TIMING

RELATIONSHIPS

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