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8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
8. AVR Memories
8.1 Overview
This section describes the different memories in the ATmega48A/PA/88A/PA/168A/PA/328/P.
The AVR architecture has two main memory spaces, the Data Memory and the Program Mem-
ory space. In addition, the ATmega48A/PA/88A/PA/168A/PA/328/P features an EEPROM
Memory for data storage. All three memory spaces are linear and regular.
8.2 In-System Reprogrammable Flash Program Memory
The ATmega48A/PA/88A/PA/168A/PA/328/P contains 4/8/16/32Kbytes On-chip In-System
Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32
bits wide, the Flash is organized as 2/4/8/16K x 16. For software security, the Flash Program
memory space is divided into two sections, Boot Loader Section and Application Program Sec-
tion in ATmega88PA and ATmega168PA. See SELFPRGEN description in section ”SPMCSR –
Store Program Memory Control and Status Register” on page 295 for more details.
The Flash memory has an endurance of at least 10,000 write/erase cycles. The
ATmega48A/PA/88A/PA/168A/PA/328/P Program Counter (PC) is 11/12/13/14 bits wide, thus
addressing the 2/4/8/16K program memory locations. The operation of Boot Program section
and associated Boot Lock bits for software protection are described in detail in ”Self-Program-
ming the Flash, ATmega 48A/48PA” on page 271 and ”Boot Loader Support – Read-While-Write
Self-Programming” on page 280. ”Memory Programming” on page 297 contains a detailed
description on Flash Programming in SPI- or Parallel Programming mode.
Constant tables can be allocated within the entire program memory address space (see the LPM
– Load Program Memory instruction description).
Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-
ing” on page 14.
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