204
8271D–AVR–05/11
ATmega48A/PA/88A/PA/168A/PA/328/P
• Bits 5:4 – UPMn1:0: Parity Mode
These bits enable and set type of parity generation and check. If enabled, the Transmitter will
automatically generate and send the parity of the transmitted data bits within each frame. The
Receiver will generate a parity value for the incoming data and compare it to the UPMn setting.
If a mismatch is detected, the UPEn Flag in UCSRnA will be set.
• Bit 3 – USBSn: Stop Bit Select
This bit selects the number of stop bits to be inserted by the Transmitter. The Receiver ignores
this setting.
• Bit 2:1 – UCSZn1:0: Character Size
The UCSZn1:0 bits combined with the UCSZn2 bit in UCSRnB sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 0 – UCPOLn: Clock Polarity
This bit is used for synchronous mode only. Write this bit to zero when asynchronous mode is
used. The UCPOLn bit sets the relationship between data output change and data input sample,
and the synchronous clock (XCKn).
Table 20-8. UPMn Bits Settings
UPMn1 UPMn0 Parity Mode
00Disabled
01Reserved
1 0 Enabled, Even Parity
1 1 Enabled, Odd Parity
Table 20-9. USBS Bit Settings
USBSn Stop Bit(s)
01-bit
12-bit
Table 20-10. UCSZn Bits Settings
UCSZn2 UCSZn1 UCSZn0 Character Size
0005-bit
0016-bit
0107-bit
0118-bit
1 0 0 Reserved
1 0 1 Reserved
1 1 0 Reserved
1119-bit
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