45
ATtiny15L
1187H–AVR–09/07
Figure 28. ADC Timing Diagram, Single Conversion
Figure 29. ADC Timing Diagram, Free Running Conversion
Sign and MSB of Result
LSB of Result
ADC Clock
ADSC
Sample & Hold
ADIF
ADCH
ADCL
Cycle Number
ADEN
1 212
13
14 15
16 17
18
19 20 21 22 23
24 25
1 2
Extended Conversion
Next
Conversion
3
MUX and REFS
Update
MUX and REFS
Update
Conversion
Complete
Table 18. ADC Conversion Time
Condition
Sample & Hold
(Cycles from Start of Conversion)
Conversion
Time (Cycles)
Conversion
Time (µs)
Extended Conversion 13.5 25.0 125 - 500
Normal Conversions 1.5 13.0 65 - 260
11 12 13
Sign and MSB of Result
LSB of Result
DC Clock
DSC
DIF
DCH
DCL
ycle Number
12
One Conversion Next Conversion
34
Conversion
Complete
Sample & Ho
MUX and REFS
Update