Avnet MicroZed - Page 11

30-Oct-2020, Rev. 1.1
10
Figure 4 – Digilent Compatible Pmod™ Interface Layout
FPGA I/O
3.3V
1
2
3
4
5
6
FPGA I/O
FPGA I/O
FPGA I/O
7
8
9
10
11
12
FPGA I/O
3.3V
FPGA I/O
FPGA I/O
FPGA I/O
Figure 5 – Digilent Pmod™ Compatible Interface Connections when VCCIO_34/35 set to
3.3V.
Table 9 – Digilent Pmod™ Compatible Interface Connections
Pmod™
Carrier
Net Name
Pmod Pin
Number
MicroHeader
Connection
Zynq AP SOC
Connection
JA
Pmod™
JA0-1 P
Pin 1
JX1, pin 11
Bank 34, T11
JA0-1 N
Pin 2
JX1, pin 13
Bank 34, T10
JA2-3 P
Pin 3
JX1, pin 12
Bank 34, T12
JA2-3 N
Pin 4
JX1, pin 14
Bank 34, U12
JA4-5 P
Pin 7
JX1, pin 18
Bank 34, V12
JA4-5 N
Pin 8
JX1, pin 20
Bank 34, W13
JA6-7 P
Pin 9
JX1, pin 23
Bank 34, T14
JA6-7 N
Pin 10
JX1, pin 25
Bank 34, T15
Pmod™
Carrier
Net Name
Pmod Pin
Number
MicroHeader
Connection
Zynq AP SOC
Connection
JB
Pmod™
JB0-1 P
Pin 1
JX1, pin 29
Bank 34, Y16
JB0-1 N
Pin 2
JX1, pin 31
Bank 34, Y17
JB2-3 P
Pin 3
JX1, pin 30
Bank 34, W14
JB2-3 N
Pin 4
JX1, pin 32
Bank 34, Y14
JB4-5 P
Pin 7
JX1, pin 35
Bank 34, T16
JB4-5 N
Pin 8
JX1, pin 37
Bank 34, U17
JB6-7 P
Pin 9
JX1, pin 36
Bank 34, V15
JB6-7 N
Pin 10
JX1, pin 38
Bank 34, W15
Pmod™
Carrier
Net Name
Pmod Pin
Number
MicroHeader
Connection
Zynq AP SOC
Connection
JC
Pmod™
JC0-1 P
Pin 1
JX1, pin 47
Bank 34, N18
JC0-1 N
Pin 2
JX1, pin 49
Bank 34, P19
JC2-3 P
Pin 3
JX1, pin 48
Bank 34, N20
JC2-3 N
Pin 4
JX1, pin 50
Bank 34, P20
JC4-5 P
Pin 7
JX1, pin 53
Bank 34, T20
JC4-5 N
Pin 8
JX1, pin 55
Bank 34, U20
JC6-7 P
Pin 9
JX1, pin 54
Bank 34, V20
JC6-7 N
Pin 10
JX1, pin 56
Bank 34, W20