The PicoZed Z7010 / Z7020 SOM (System-On-Module) is a low-cost, versatile System-On-Module designed for a broad range of applications. It integrates a Xilinx Zynq-7000 All Programmable SoC, memory, and various interfaces, making it a powerful and flexible solution for embedded systems.
Function Description:
The core of the PicoZed Z7010 / Z7020 SOM is a Xilinx XC7Z010-1CLGG400 or XC7Z020-1CLG400 AP SoC, available in both commercial and industrial temperature grades. This SoC combines a processing system (PS) with programmable logic (PL), offering a highly integrated platform for diverse applications. The PS includes a hardened memory interface unit with a dynamic memory controller and static memory interface modules.
The module supports multiple configuration modes, with Quad-SPI Flash as the primary default. Auxiliary configuration options include eMMC for a second-stage bootloader, and via an End User Carrier Card, JTAG, or microSD/SD Card. This flexibility allows users to choose the most suitable boot method for their application.
The PicoZed SOM provides a comprehensive set of interfaces to connect to external peripherals and expansion cards. These include a 10/100/1000 Ethernet PHY and a USB 2.0 OTG PHY, both requiring connectors on the end-user carrier card. Three 100-pin Micro Headers (FCI, 61082-101400LF) serve as the primary connection points to expansion cards, carrying PL and PS I/O, dedicated analog inputs, JTAG signals, power, and control signals. The JX1 and JX2 headers primarily handle PL and PS I/O, while JX3 is dedicated to peripheral interfaces like Ethernet, USB 2.0, and additional PL I/O (for the Zynq 7020 devices).
The module's power system is designed for efficiency and flexibility. It incorporates high-efficiency regulators for various internal voltage rails (VCCINT, VCCPINT, VCCBRAM, VCCAUX, VCCPAUX, VCCPLL, VCCO_0, VCCO_DDR, VCCO_MIO1, and VCCO_MIO0). Other bank voltages (VCCO_34, VCCO_35, and VCCO_13) are supplied from the expansion card via the Micro Headers, allowing the carrier card to control these I/O bank voltages independently.
Important Technical Specifications:
- SoC: Xilinx XC7Z010-1CLGG400 or XC7Z020-1CLG400 AP SoC.
- Memory:
- 1 GB DDR3 (x32) with speeds up to 1,066 MT/s. The DDR3L interface uses 1.35V SSTL-compatible inputs by default, with an option for 1.5V DDR3 devices.
- 128 Mb Quad-SPI Flash (Spansion S25FL128S) for non-volatile boot, application code, and data storage. Supports x1, x2, and x4 modes, and speeds up to 104 MHz (400Mbs in Quad-SPI mode).
- 4 GB eMMC (Micron MTFC4GMDEA-4M IT eMMC) for non-volatile user data storage. Features a 4-bit data interface and 52MHz max clock speed.
- Oscillator: On-board 33.333 MHz oscillator for the PS. A 24 MHz Abracon ASDMB CMOS oscillator is used for the USB ULPI interface.
- Interfaces:
- 10/100/1000 Ethernet PHY (Marvell 88E1512) with RGMII interface, operating at 1.8V.
- USB 2.0 OTG PHY (SMSC USB3320) with 8-bit ULPI interface, supporting speeds up to 480Mbs, operating at 1.8V.
- Three 100-pin Micro Headers (FCI, 61082-101400LF) for expansion.
- I/O:
- 20 PS MIO pins (8 from bank 500, 12 from bank 501) for peripherals like USB, SPI, SDIO, CAN, UART, I2C, or general-purpose I/O.
- 100 PL I/O pins on the 7010 (50 from bank 34, 50 from bank 35).
- 125 PL I/O pins on the 7020 (additional 25 from bank 13).
- Differential LVDS pairs on banks 34 and 35 are capable of 950Mbps DDR data.
- Power Rails (on-board regulators): 1.0V, 1.35V, 1.8V, 3.3V, and 0.675V.
- Dimensions: 2.25" x 4.00" (57.15 mm x 101.6 mm), maximum vertical dimension of 0.366" (9.3mm).
Usage Features:
- Flexible Configuration: The PicoZed SOM offers multiple boot options, including QSPI Flash (default), eMMC, JTAG, and SD Card, providing adaptability for different application requirements. Jumper and switch settings allow easy selection of the desired boot mode.
- Extensive I/O: With a significant number of PS MIO and PL I/O pins routed to the Micro Headers, the module supports a wide array of custom interfaces and peripherals on a carrier card. The PL I/O pins are routed with matched lengths, suitable for both single-ended and differential pairs (LVDS).
- Carrier Card Integration: The design emphasizes integration with an end-user carrier card. The carrier card is responsible for providing VCCO voltages for PL I/O banks (34, 35, and 13), allowing designers to customize voltage levels and standards. The USB and Ethernet PHY connectors are also intended to reside on the carrier card.
- Software Control: The eMMC I/O can be multiplexed with JX2 MIO pins, and the Zynq PS_MIO0 pin can be used for software control to select between eMMC and standard MIO interfaces in real-time. This offers flexibility in how these pins are utilized by the application.
- Power Sequencing: The module implements a defined power supply sequencing, with 1.0V, 1.8V, DDR3L (1.35V), and 3.3V rails coming up in sequence. The
PG_MODULE signal, driven by the 3.3V power good output, acts as the power-on reset control for the Zynq and other PHYs.
- Design Tool Support: It is recommended to use the Vivado Design Suite for custom interface implementation, place and route, and timing closure, ensuring design integrity.
Maintenance Features:
- Power Good LED: A green status LED (D1) illuminates when the U18 3.3V power rail is stable, indicating that all on-board regulators are operational. This provides a quick visual check for power system health.
- Reset Signals: The Zynq PS_POR_B (Power-on Reset) is the master reset for the entire chip, connected to the power good output of the final power regulation stage. Other reset signals like PROGRAM_B, DONE, PUDC_B, and INIT_B are routed to the carrier card via Micro Headers, allowing external control and monitoring.
- JTAG Connections: JTAG signals are routed to the JX1 Micro Header, enabling external JTAG cable connections for debugging and configuration operations. The Zynq Bank 0 reference voltage (VCCO_0) is 3.3V, and the carrier card's JTAG Vref should match for compatibility.
- Power Estimation: For designs with varying power consumption, Xilinx Power Estimator (XPE) tool is recommended to estimate power consumption, aiding in carrier card power supply sizing and thermal management.
- Battery Backup: The VCCBATT rail supports a battery backup for maintaining an encryption key in battery-backed RAM for device secure boot. If not used, VCCBATT can be tied to ground or VCCAUX. An optional 0-ohm resistor (R14) can be removed to connect an external battery from the carrier card.
- Cooling Fan Option: An unpopulated header (JP1, labeled FAN) is available for connecting a cooling fan for high-performance designs. It provides ground connections and a VIN voltage connection. A resistor option for a 3.3V fan (JT3) is also provided. Mounting holes are included for securing active or passive heat sinks.
Need help?
To Next Page
General
