Avnet PicoZed 7010 User Manual

3-Feb-2015
12
The diagrams listed below illustrate the connections on the Micro Headers.
Table 8 – Micro Header JX1 and JX2 Pin Outs
Micro Header #1 (JX1)
Micro Header #2 (JX2)
Signal Name
Source
Pins
Signal Name
Source
Pins
PL
Bank 34 I/Os
(Except for
PUDC_B)
Zynq Bank 34
49
PL
Bank 35 I/Os
Zynq Bank 35
50
Bank 13 pins
(PicoZed 7020)
Bank 13
8
Bank 13 pins
(PicoZed 7020)
Bank 13
7
JTAG
TMS_0
Zynq Bank 0
5
PS
PS Pmod
MIO[0,9-15]
Zynq Bank 500
8
TDI_0
Zynq Bank 0
TCK_0
Zynq Bank 0
C
Init_B_0
Zynq Bank 0
1
TDO_0
Zynq Bank 0
Power
PG_1V8
Expansion
1
Carrier_SRST#
Expansion
PG_MODULE
Expansion
1
Analog
VP_0
Zynq Bank 0
4
Vin
Expansion
5
VN_0
Zynq Bank 0
GND
Expansion
23
DXP_0
Zynq Bank 0
VCCO_35
Expansion
3
DXN_0
Zynq Bank 0
VCCO_13
Expansion
1
C
FPGA_DONE
Zynq Bank 0
2
PUDC_B / IO
Zynq Bank 34
TOTAL
100
PWR_Enable
Expansion
1
Vin
Expansion
4
GND
Expansion
23
VCCO_34
Expansion
3
VBATT
Expansion
1
TOTAL
100
Table 9 – Micro Header JX3 Pin Out
Micro Header #3 (JX3)
Signal Name
Source
Pins
PL
Bank 13 I/Os
(PicoZed 7020)
Zynq Bank 13
(PicoZed 7020)
20*
PS
Ethernet I/O
501
10
USB I/O
501
4
PS MIO[40-51]
Zynq Bank 501
12
MGT
(No Connect)
No Connect
20
Power
MGT_AVCC (No Connect)
No Connect
4
MGTAVTT (No Connect)
No Connect
2
VCCO_13
Expansion
2
GND
Expansion
25
USB_VBUS_OTG
Expansion
1
TOTAL
100
* PicoZed 7020 only populates 10 out of 20 JX3 IO Dedicated to Bank 13 Signals

Avnet PicoZed 7010 Specifications

General

Brand	Avnet
Model	PicoZed 7010
Category	Control Unit
Language	English