Clevo NL50MU - Processor 3;12

5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CMD
SINGLE=45ohm
SINGLE=50ohm
SINGLE=45ohm
CTRL
STROBE
DIFF=90ohm
CTRL
CLOCK
SINGLE=45ohm
DIFF=85ohm
DATA
SINGLE=50ohm
A0
M_B_DQS#0
M_B_DQS#1
M_B_DQS#2
M_B_DQS#3
M_B_DQS#4
M_B_DQS#5
M_B_DQS#6
M_B_DQS#7
M_B_DQS7
M_B_DQS1
M_B_DQS#6
M_B_DQS6
M_B_DQS5
M_B_DQS4
M_B_DQS3
M_B_DQS#2
M_B_DQS2
M_B_DQS0
M_B_DQS#7
M_B_DQS#5
M_B_DQS#4
M_B_DQS#3
M_B_DQS#1
M_B_DQS#0
M_B_A2
M_B_A4
M_B_A3
M_B_A0
M_B_A1
M_B_A5
M_B_A10
M_B_A9
M_B_A7
M_B_A6
M_B_A16
M_B_A8
M_B_A11
M_B_A12
M_B_A13
M_B_A14
M_B_A15
M_B_DQ_0_0[15]
M_B_DQ_1_0[15]
M_B_DQ_1_1[15]
M_B_DQ_1_2[15]
M_B_DQ_1_3[15]
M_B_DQ_1_4[15]
M_B_DQ_1_5[15]
M_B_DQ_1_6[15]
M_B_DQ_1_7[15]
M_B_DQ_0_1[15]
M_B_DQ_0_2[15]
M_B_DQ_0_3[15]
M_B_DQ_0_4[15]
M_B_DQ_0_5[15]
M_B_DQ_0_6[15]
M_B_DQ_0_7[15]
M_B_DQ_2_0[15]
M_B_DQ_2_1[15]
M_B_DQ_2_2[15]
M_B_DQ_2_3[15]
M_B_DQ_2_4[15]
M_B_DQ_2_5[15]
M_B_DQ_2_6[15]
M_B_DQ_2_7[15]
M_B_DQ_3_0[15]
M_B_DQ_4_0[15]
M_B_DQ_5_0[15]
M_B_DQ_3_1[15]
M_B_DQ_3_2[15]
M_B_DQ_3_3[15]
M_B_DQ_3_4[15]
M_B_DQ_3_5[15]
M_B_DQ_3_6[15]
M_B_DQ_3_7[15]
M_B_DQ_4_1[15]
M_B_DQ_4_2[15]
M_B_DQ_4_3[15]
M_B_DQ_4_4[15]
M_B_DQ_4_5[15]
M_B_DQ_4_6[15]
M_B_DQ_4_7[15]
M_B_DQ_6_0[15]
M_B_DQ_7_0[15]
M_B_DQ_5_1[15]
M_B_DQ_5_2[15]
M_B_DQ_5_3[15]
M_B_DQ_5_4[15]
M_B_DQ_5_5[15]
M_B_DQ_5_6[15]
M_B_DQ_5_7[15]
M_B_DQ_6_1[15]
M_B_DQ_6_2[15]
M_B_DQ_6_3[15]
M_B_DQ_6_4[15]
M_B_DQ_6_5[15]
M_B_DQ_6_6[15]
M_B_DQ_6_7[15]
M_B_DQ_7_1[15]
M_B_DQ_7_2[15]
M_B_DQ_7_3[15]
M_B_DQ_7_4[15]
M_B_DQ_7_5[15]
M_B_DQ_7_6[15]
M_B_DQ_7_7[15]
M_B_DQS#[7:0] [15]
M_B_CLK_DDR1 [15]
M_B_CLK_DDR#1 [15]
M_B_CLK_DDR#0 [15]
M_B_CLK_DDR0 [15]
M_B_CKE1 [15]
M_B_CKE0 [15]
M_B_CS#1 [15]
M_B_CS#0 [15]
M_B_DQS[7:0] [15]
M_B_ODT0 [15]
M_B_ODT1 [15]
M_B_A[16:0] [15]
DDR1_B_ALERT# [15]
DDR1_B_PARITY [15]
M_B_BA0 [15]
M_B_BA1 [15]
M_B_BG0 [15]
M_B_BG1 [15]
M_B_ACT# [15]
DDR1_VREF_CA [15]
Title
Size Document Number Re v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[04] TGL U -C / DDR CHB
A3
447Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Re v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[04] TGL U -C / DDR CHB
A3
447Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number Re v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[04] TGL U -C / DDR CHB
A3
447Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
LP4-LP5(NIL)/DDR4 (NIL)/DDR4 (IL)
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
DDR4/LP4/LP5/LP5 CMD Flip
U21C
TGL_U_IP_EXT
DDR1_VREF_CA
AU52
DDR1_MA3/DDR4_CS1/DDR4_CS0/DDR4_CA3
AA53
DDR1_ODT1/DDR5_CA0/DDR5_CA0/DDR5_CA6
AE44
DDR1_CKE1/DDR6_CA4/DDR6_CA5/DDR6_CA1
P52
NC/DDR5_CLK_N/DDR5_CLK_N/DDR5_CLK
AC41
DDR7_DQ1_0/DDR1_DQ7_0/DDR1_DQ7_0
N38
DDR7_DQ1_5/DDR1_DQ7_5/DDR1_DQ7_5
H36
DDR7_DQ0_0/DDR1_DQ6_0/DDR1_DQ6_0
J47
DDR7_DQ0_5/DDR1_DQ6_5/DDR1_DQ6_5
J41
DDR6_DQ1_0/DDR1_DQ5_0/DDR0_DQ7_0
A40
DDR6_DQ1_5/DDR1_DQ5_5/DDR0_DQ7_5
B38
DDR6_DQ0_0/DDR1_DQ4_0/DDR0_DQ6_0
E47
DDR6_DQ0_5/DDR1_DQ4_5/DDR0_DQ6_5
D43
DDR5_DQ1_0/DDR1_DQ3_0/DDR1_DQ5_0
AL47
DDR5_DQ1_5/DDR1_DQ3_5/DDR1_DQ5_5
AL41
DDR5_DQ0_0/DDR1_DQ2_0/DDR1_DQ4_0
AV47
DDR5_DQ0_5/DDR1_DQ2_5/DDR1_DQ4_5
AR42
DDR4_DQ1_0/DDR1_DQ1_0/DDR0_DQ5_0
AH49
DDR4_DQ1_5/DDR1_DQ1_5/DDR0_DQ5_5
AF50
DDR4_DQ0_0/DDR1_DQ0_0/DDR0_DQ4_0
AP49
DDR4_DQ0_5/DDR1_DQ0_5/DDR0_DQ4_5
AL50
DDR1_MA1/NC/DDR4_CS1/DDR4_CA4
AC52
NC/DDR4_CKE0/DDR4_WCK_P/DDR4_WCK_P
W51
NC/DDR5_CKE0/DDR5_WCK_P/DDR5_WCK_P
AC47
DDR7_DQ1_3/DDR1_DQ7_3/DDR1_DQ7_3
N36
DDR7_DQ0_3/DDR1_DQ6_3/DDR1_DQ6_3
G45
DDR6_DQ1_3/DDR1_DQ5_3/DDR0_DQ7_3
E41
DDR6_DQ0_3/DDR1_DQ4_3/DDR0_DQ6_3
A46
DDR5_DQ1_3/DDR1_DQ3_3/DDR1_DQ5_3
AJ45
DDR5_DQ0_3/DDR1_DQ2_3/DDR1_DQ4_3
AR45
DDR4_DQ1_3/DDR1_DQ1_3/DDR0_DQ5_3
AH53
DDR4_DQ0_3/DDR1_DQ0_3/DDR0_DQ4_3
AP53
DDR1_CLK_P1/DDR7_CLK_P/DDR7_CLK_P/DDR7_CLK_P
R41
DDR1_MA11/NC/DDR6_CS1/DDR6_CA4
N51
NC/DDR6_CS0/DDR6_CA2/DDR6_CA2
J53
NC/DDR6_CKE0/DDR6_WCK_P/DDR6_WCK_P
K51
NC/DDR5_CLK_P/DDR5_CLK_P/DDR5_CLK_P
AC42
DDR7_DQ1_1/DDR1_DQ7_1/DDR1_DQ7_1
L38
DDR7_DQ1_2/DDR1_DQ7_2/DDR1_DQ7_2
L36
DDR7_DQ1_6/DDR1_DQ7_6/DDR1_DQ7_6
G36
DDR7_DQ1_7/DDR1_DQ7_7/DDR1_DQ7_7
G38
DDR7_DQ0_1/DDR1_DQ6_1/DDR1_DQ6_1
G47
DDR7_DQ0_2/DDR1_DQ6_2/DDR1_DQ6_2
J45
DDR7_DQ0_6/DDR1_DQ6_6/DDR1_DQ6_6
G41
DDR7_DQ0_7/DDR1_DQ6_7/DDR1_DQ6_7
G42
DDR6_DQ1_1/DDR1_DQ5_1/DDR0_DQ7_1
B40
DDR6_DQ1_2/DDR1_DQ5_2/DDR0_DQ7_2
D40
DDR6_DQ1_6/DDR1_DQ5_6/DDR0_DQ7_6
D38
DDR6_DQ1_7/DDR1_DQ5_7/DDR0_DQ7_7
E38
DDR6_DQ0_1/DDR1_DQ4_1/DDR0_DQ6_1
D46
DDR6_DQ0_2/DDR1_DQ4_2/DDR0_DQ6_2
B46
DDR6_DQ0_6/DDR1_DQ4_6/DDR0_DQ6_6
B43
DDR6_DQ0_7/DDR1_DQ4_7/DDR0_DQ6_7
A43
DDR5_DQ1_1/DDR1_DQ3_1/DDR1_DQ5_1
AL45
DDR5_DQ1_2/DDR1_DQ3_2/DDR1_DQ5_2
AJ47
DDR5_DQ1_6/DDR1_DQ3_6/DDR1_DQ5_6
AJ42
DDR5_DQ1_7/DDR1_DQ3_7/DDR1_DQ5_7
AJ41
DDR5_DQ0_1/DDR1_DQ2_1/DDR1_DQ4_1
AR47
DDR5_DQ0_2/DDR1_DQ2_2/DDR1_DQ4_2
AV45
DDR5_DQ0_6/DDR1_DQ2_6/DDR1_DQ4_6
AV42
DDR5_DQ0_7/DDR1_DQ2_7/DDR1_DQ4_7
AR41
DDR4_DQ1_1/DDR1_DQ1_1/DDR0_DQ5_1
AH50
DDR4_DQ1_2/DDR1_DQ1_2/DDR0_DQ5_2
AH52
DDR4_DQ1_6/DDR1_DQ1_6/DDR0_DQ5_6
AF52
DDR4_DQ1_7/DDR1_DQ1_7/DDR0_DQ5_7
AF53
DDR4_DQ0_1/DDR1_DQ0_1/DDR0_DQ4_1
AP50
DDR4_DQ0_2/DDR1_DQ0_2/DDR0_DQ4_2
AP52
DDR4_DQ0_6/DDR1_DQ0_6/DDR0_DQ4_6
AL52
DDR4_DQ0_7/DDR1_DQ0_7/DDR0_DQ4_7
AL53
DDR1_MA5/DDR4_CA5/DDR4_CA6/DDR4_CA0
U50
DDR1_ALERT#
AU53
DDR1_BG0/DDR6_CA3/DDR6_CA4/DDR6_CS1
J52
DDR1_MA4/DDR4_CS0/DDR4_CA2/DDR4_CA2
AA51
DDR1_CS1/DDR5_CA1/DDR4_CA1/DDR4_CA5
AE42
DDR1_CLK_P0/DDR4_CLK_P/DDR4_CLKP/DDR4_CLK_P
Y52
DDR1_BA1/DDR5_CA5/DDR5_CA6/DDR5_CA0
AA42
DDR1_MA6/DDR4_CA3/DDR4_CA4/DDR4_CS1
U52
DDR1_MA8/DDR4_CA2/DDR4_CA3/DDR4_CS0
U53
DDR1_MA13/DDR5_CS1/DDR5_CS0/DDR5_CA3
AE41
DDR1_MA10/DDR7_CA1/DDR7_CA1/DDR7_CA5
U42
DDR1_MA15/DDR5_CA3/DDR5_CA4/DDR5_CS1
AA44
DDR4_DQSP_0/DDR1_DQSP_0/DDR0_DQSP_4
AN51
DDR4_DQSP_1/DDR1_DQSP_1/DDR0_DQSP_5
AG51
DDR5_DQSP_0/DDR1_DQSP_2/DDR1_DQSP_4
AV44
DDR5_DQSP_1/DDR1_DQSP_3/DDR1_DQSP_5
AJ44
DDR6_DQSP_0/DDR1_DQSP_4/DDR0_DQSP_6
C45
DDR6_DQSP_1/DDR1_DQSP_5/DDR0_DQSP_7
D39
DDR7_DQSP_0/DDR1_DQSP_6/DDR1_DQSP_6
G44
DDR7_DQSP_1/DDR1_DQSP_7/DDR1_DQSP_7
K36
DDR1_CKE0/DDR6_CA5/DDR6_CA6/DDR6_CA0
J50
NC/DDR4_CKE1/DDR4_WCK_N/DDR4_W CK
W53
NC/DDR5_CKE1/DDR5_WCK_N/DDR5_W CK
AC45
NC/DDR6_CKE1/DDR6_WCK_N/DDR6_W CK
K53
NC/DDR7_CKE1/DDR7_WCK_N/DDR7_W CK
R45
DDR1_MA7/DDR4_CA4/DDR4_CA5/DDR4_CA1
W50
DDR1_MA9/DDR6_CA0/DDR6_CA0/DDR6_CA6
P50
DDR1_BG1/DDR6_CA2/DDR6_CA3/DDR6_CS0
K50
DDR4_DQSN_0/DDR1_DQSN_0/DDR0_DQSN_4
AN50
DDR4_DQSN_1/DDR1_DQSN_1/DDR0_DQSN_5
AG50
DDR5_DQSN_0/DDR1_DQSN_2/DDR1_DQSN_4
AR44
DDR5_DQSN_1/DDR1_DQSN_3/DDR1_DQSN_5
AL44
DDR6_DQSN_0/DDR1_DQSN_4/DDR0_DQSN_6
D45
DDR6_DQSN_1/DDR1_DQSN_5/DDR0_DQSN_7
C39
DDR7_DQSN_0/DDR1_DQSN_6/DDR1_DQSN_6
J44
DDR7_DQSN_1/DDR1_DQSN_7/DDR1_DQSN_7
K38
DDR1_ACT#/DDR6_CS1/DDR6_CS0/DDR6_CA3
N53
DDR1_MA16/DDR5_CA4/DDR5_CA5/DDR5_CA1
AA47
DDR1_PAR/DDR7_CS1/DDR7_CS0/DDR7_CA3
U45
DDR1_ODT0/DDR5_CS0/DDR5_CA2/DDR5_CA2
AE45
NC/DDR4_CA0/DDR4_CA0/DDR4_CA6
AC53
NC/DDR4_CA1/DDR4_CA1/DDR4_CA5
AC50
NC/DDR7_CA2/DDR7_CA3/DDR7_CS0
N47
NC/DDR7_CA3/DDR7_CA4/DDR7_CS1
N44
NC/DDR7_CKE0/DDR7_WCK_P/DDR7_WCK_P
R47
DDR1_CLK_N0/DDR4_CLK_N/DDR4_CLK_N/DDR4_CLK
Y53
NC/DDR6_CLK_N/DDR6_CLK_N/DDR6_CLK
M53
DDR1_CLK_N1/DDR7_CLK_N/DDR7_CLK_N/DDR7_CLK
R42
DDR1_CS0/NC/DDR4_CS1/DDR4_CA4
AE47
NC/DDR6_CLK_P/DDR6_CLK_P/DDR6_CLK_P
M52
DDR1_BA0/DDR7_CA0/DDR7_CA0/DDR7_CA6
U44
DDR1_MA2/DDR7_CS0/DDR7_CA2/DDR7_CA2
U47
DDR1_MA12/DDR6_CA1/DDR6_CA1/DDR6_CA5
P53
DDR1_MA14/DDR5_CA2/DDR5_CA3/DDR5_CS0
AA45
DDR7_DQ1_4/DDR1_DQ7_4/DDR1_DQ7_4
H38
DDR7_DQ0_4/DDR1_DQ6_4/DDR1_DQ6_4
J42
DDR6_DQ1_4/DDR1_DQ5_4/DDR0_DQ7_4
A38
DDR6_DQ0_4/DDR1_DQ4_4/DDR0_DQ6_4
E44
DDR5_DQ1_4/DDR1_DQ3_4/DDR1_DQ5_4
AL42
DDR5_DQ0_4/DDR1_DQ2_4/DDR1_DQ4_4
AV41
DDR4_DQ1_4/DDR1_DQ1_4/DDR0_DQ5_4
AF49
DDR4_DQ0_4/DDR1_DQ0_4/DDR0_DQ4_4
AL49
DDR1_MA0/NC/DDR7_CS1/DDR7_CA4
U41
NC/DDR7_CA4/DDR7_CA5/DDR7_CA1
N45
NC/DDR7_CA5/DDR7_CA6/DDR7_CA0
N42
Sheet 4 of 47
Processor 3/12
Schematic Diagrams
Processor 3/12 B - 5
B.Schematic Diagrams
Processor 3/12