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Clevo NL50MU - Processor 10;12

Clevo NL50MU
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Schematic Diagrams
Processor 9/12 B - 11
B.Schematic Diagrams
Processor 9/12
Sheet 10 of 47
Processor 9/12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Tiger Lake U K/20 POWER CONTROL
LOW-> 3.3 V
HIGH-> 1.8 V
NO TERMINATION
NOT SAMPLED
DEFAULT 3.3V
Modern Standby
Modern Standby
PLT_RST# to Buffer
Power sequence tCPU08
oscar 07_08_2020
OSCAR 07_24_2020
A0
D02 modify
20210617
PWR_BTN#
RSMRST#
SYS_PWROK
PCH_PWROK
PCH_DPWROK
PCH_PWROK_EC
PCH_PWROK
SYS_RESET#
SYS_PWROK
RSMRST#
SYS_RESET#
PLT_RST#
SUSC#_PCH
SLP_S5#
SLP_S0#
SUSB#_PCH
SLP_SUS#_R
PCH_PWROK_EC SYS_PWROK
PCH_PWROK
SPIVCCIOSEL
SLP_A#
CPU_C10_GATE#
PROCPWRGD
PWR_BTN#
PM_BATLOW#
VCCST_PWRGD H_VCCST_PWRGD
ALL_SYS_PWRGD
VCCST_PG#
AC_PRESENT
EXT_PWR_GATE2#
PCIE_WAKE#
LAN_WAKEUP#
LAN_DISABLE#
VCCST_OVERRIDE
VCCST_OVERRIDE
VCCST_OVERRIDE
PLT_RST#
VCCIO_EN
ALL_SYS_PWRGD
GPD7_REST
SUSC#_PCH
SUSB#_PCH
PCH_PWROK
ALL_SYS_PWRGD
AC_PRESENT
PM_BATLOW#
SLP_SUS#
EXT_PWR_GATE#
EXT_PWR_GATE#
GPD7_REST
PCH_DPWROKPCH_DPWROK_EC
SLP_WLAN#
3.3VS
3.3V
VCCST
3.3VA
3.3VA
VDD3
3.3VS
3.3V
3.3V
3.3V
3.3VS
3.3VA
3.3V
3.3V
3.3V
VDD3
3.3VS
RSMRST#[10,24]
SUSC#_PCH[24]
SLP_S0#[24,33]
SUSB#_PCH[24]
SLP_SUS#[24,31]
PCH_PWROK_EC[24]
SM_INTRUDER#[9]
CPU_C10_GATE# [24,33]
PWR_BTN# [24]
AC_PRESENT [24]
3.3_VCCST_OVERRIDE [33]
PCH_DPWROK_EC[24]
BUF_PLT_RST# [22,24,25,26,29]
SUSB#[10,17,23,28,33,36]
RSMRST#[10,24]
VDDQ_PWRGD[31]
ALL_SYS_PWRGD [17,24,38]EC_EN[24]
SUSC# [33]
SUSB# [10,17,23,28,33,36]
PM_PWROK[24]
H_VR_READY[38]
LAN_WAKEUP# [29]
LAN_DISABLE# [29]
PM_SLP_LAN#[29]
PCIE_WAKE# [26]
EC_PCIE_WAKE# [24,25,29]
Title
Size Document Number Re v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[10] TGL UP3 L POWER CONTROL
A3
10 47Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
NLx0MU
Title
Size Document Number Re v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[10] TGL UP3 L POWER CONTROL
A3
10 47Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
NLx0MU
Title
Size Document Number Re v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[10] TGL UP3 L POWER CONTROL
A3
10 47Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
NLx0MU
R90 0_04
R235 *10K_04
R211 1K_04
U29B
74LVC08APW
4
5
6
147
S
D
G
Q7A
MTDK3S6R
2
61
R259 *100K_04
S
D
G
Q7B
MTDK3S6R
5
34
U29D
74LVC08APW
12
13
11
147
R134 *100K_04
R142 100K_04
U21L
TGL_U_IP_EXT
DSW_PW ROK
DK35
SYS_PWROK
DF10
PCH_PWROK
DN35
SPIVCCIOSEL
DT49
VCCSTPWRGOOD_TCSS
CE5
VCCST_PWRGD
BP8
VCCST_OVERRIDE
BP9
INTRUDER#
DM37
GPP_H3/SX_EXIT_HOLDOFF#
DG31
GPD2/LAN_WAKE#
DM41
WAKE#
DK39
GPD3/PW RBTN#
DK41
SLP_SUS#
DV49
GPP_B12/SLP_S0#
DD42
GPD9/SPL_W LAN#
DT44
GPD4/SLP_S3#
DJ43
GPP_F21/EXT_PW R_GATE2#
DW12
GPD6/SLP_A#
DR41
GPD5/SLP_S4#
DJ41
GPD7
DN43
GPP_B11/PMCALERT#
CW40
SLP_LAN#
DN39
GPD11/LANPHYPC/DSWLDO_MON
DT41
GPP_B13/PLTRST#
DD41
GPP_H18/CPU_C10_GATE#
DN27
PROCPWRGD
BM9
RSMRST#
DM35
GPP_F20/EXT_PW R_GATE#
DR12
GPD1/ACPRESENT
DK43
SYS_RESET#
DD10
GPD0/BATLOW #
DN41
GPD10/SLP_S5#
DM43
R496 *100K_04
R88
1K_04
U29A
74LVC08APW
1
2
3
147
R151
100K_04
R203 8.2K_04
R479 *100K_04
R450 0_04
R133 *3.3K_1%_04
R497 *100K_04
R196 *14mil_02
R195 10K_04
R188 *10K_04
R535
61.9K_1%_04
R126 10K_04
R91
1M_04
C420 0.1u_6.3V_X5R_02
T39
R187 *100K_04
U29C
74LVC08APW
9
10
8
147
R448
100K_1%_04
R86 *1K_04
R127 *14mil_02
R447
100K_1%_04
C188 0.1u_6.3V_X5R_02
R193 *100K_04
R192 100K_04
R212 100K_04
R208 4.7K_04
R201 100K_04
U5
74AHC1G08GW
1
2
5
4
3
R446
100K_04
T42
R517 *14mil_02
T13
R220 *0_04
Q27
MMBT3904H
B
E C
Q26
2SK3018S3
G
DS
R480 100K_04
R141
100K_04
R530 0_04
R485
0_04
R87 60.4_1%_04
U6
74AHC1G08GW
1
2
5
4
3
C116
*0.01u_50V_X7R_04
R449
100K_04
R523 *0_04
R173 *4.7K_04

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