5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG[0]: Stall reset sequence after
Ʉ
PCU PLL
lock until de-asserted:
— 1 = (Default) Normal Operation; No
stall.
— 0 = Stall.
CFG[1]: Reserved configuration lane.
Ʉ
CFG[2]: PCI Express* Static x16 Lane
Ʉ
Numbering Reversal.
— 1 = Normal operation
— 0 = Lane numbers reversed.
CFG[3]: Reserved configuration lane.
Ʉ
CFG[4]: eDP enable:
Ʉ
— 1 = Disabled.
— 0 = Enabled.
CFG[6:5]: PCI Express* Bifurcation
Ʉ
— 00 = 1 x8, 2 x4 PCI Express*
— 01 = reserved
— 10 = 2 x8 PCI Express*
— 11 = 1 x16 PCI Express*
CFG[7]: PEG Training:
Ʉ
— 1 = (default) PEG Train immediately
following RESET# de assertion.
— 0 = PEG Wait for BIOS for training.
CFG[19:8]: Reserved configuration
Ʉ
lanes.
1.8V/3.3V:GPIO_A B C D E F H R T U
1.8V:GPIO_S
3.3V:GPD
0=>Enable security measures defined
in the Flash Descriptor.(Default)
1=>Disable Flash Descriptor
Security (override).
A0
STRAP PIN
Flash Descriptor Security Overide
Low = Enable security measures defined in the Flash Descriptor.
(Default)
High = Disable Flash Descriptor Security (override)
20191111(D02B)
⺈⓮⺢嬘
3/15
BPM#0
NCTF_C1
NCTF_D2
CFG14
SKTOCC#
CFG_RCOMP
MBIAS_RCOMP
CFG0
CFG4
CFG6
CFG5
CFG3
CFG7
SNDW_RCOMP
PCH_TP1
PCH_TP0
IST_TP1
IST_TP0
HDA_SDOUT_R
NCTF_A51
NCTF_B51
NCTF_DW3
NCTF_DW2
NCTF_DV2
NCTF_E1
NCTF_F1
NCTF_DW52
NCTF_DV53
HDA_SDOUT_R
HDA_BITCLK#L
HDA_SYNC#L
HDA_RST#1
HDA_SDIN0
HDA_BITCLK#L
HDA_SYNC#L
HDA_SDIN0
HDA_RST#1
3.3VA
3.3VA
CNVI_RST# [25]
PCH_BT_EN [25]
USB_TYPE[29]
ME_WE [24]
INTP_OUT [19]
CNVI_CLKREQ [25]
Title
Size Document Number R e v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[07] TGL U -G,S,T / SPI,SMB,ESPI
A3
747Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number R e v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[07] TGL U -G,S,T / SPI,SMB,ESPI
A3
747Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
Title
Size Document Number R e v
Date: Sheet
of
6-71-NLx0MU-D02
D02
[07] TGL U -G,S,T / SPI,SMB,ESPI
A3
747Wednesday, August 18, 2021
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
U21S
TGL_U_IP_EXT
RSVD_23
C53
RSVD_22
DF49
RSVD_21
DF50
RSVD_20
DF52
RSVD_27
U35
IST_TP_1
A6
RSVD_30
AP9
RSVD_26
CF39
IST_TP_0
A4
RSVD_31
A52
RSVD_25
E53
RSVD_32
CB39
RSVD_24
T35
PCH_IST_TP_0
DU53
PCH_IST_TP_1
DT52
RSVD_29
B53
RSVD_19
DF53
RSVD_28
F53
RSVD_TP_29
V21
RSVD_TP_28
BF12
RSVD_TP_27
D4
RSVD_TP_26
CY15
RSVD_TP_25
CY30
RSVD_TP_39
CY28
RSVD_TP_38
U38
RSVD_TP_37
W38
RSVD_TP_36
AY12
RSVD_TP_35
W37
RSVD_TP_34
BB12
RSVD_TP_33
U21
RSVD_TP_32
CD39
RSVD_TP_31
U37
RSVD_TP_30
W20
T7
R488 *0_02
T28
T34
U21T
TGL_U_IP_EXT
RSVD_15
DV6
RSVD_TP_9
C1
BPM#_0
Y2
CFG_4
E6
VSS_1
DV51
RSVD_12
AK9
BPM#_1
AB4
CFG_5
H9
RSVD_13
AH9
CFG_6
K8
RSVD_10
DD13
CFG_7
H7
RSVD_11
DF13
CFG_17
U17
CFG_0
E7
CFG_16
H11
CFG_1
D9
CFG_RCOMP
B5
CFG_2
E9
CFG_15
T15
TP_4
DV53
CFG_3
H5
CFG_14
V17
CFG_13
U15
TCP0_MBIAS_RCOMP
AR2
RSVD_7
B3
CFG_12
K11
SKTOCC#
D52
RSVD_TP_2
AL10
RSVD_6
A3
CFG_11
K12
RSVD_18
V35
RSVD_TP_3
AM12
CFG_10
K9
RSVD_TP_4
AH12
CFG_8
K7
RSVD_TP_19
E1
RSVD_TP_18
DV2
RSVD_TP_17
DW2
RSVD_TP_16
DT2
RSVD_TP_15
DU1
RSVD_TP_14
DW3
RSVD_TP_13
DV4
RSVD_TP_12
CU40
RSVD_TP_11
CP39
RSVD_TP_10
D2
RSVD_TP_5
AJ10
CFG_9
T17
TP_3
DW52
RSVD_TP_24
DW5
RSVD_TP_23
DR53
RSVD_TP_22
DR2
RSVD_TP_21
DR1
RSVD_16
AB2
RSVD_TP_20
F1
RSVD_TP_6
AR1
RSVD_17
W34
RSVD_TP_7
A51
RSVD_9
BM12
BPM#_2
M4
RSVD_14
DW6
RSVD_TP_8
B51
RSVD_8
BN10
BPM#_3
Y1
T16
R137 200_1%_04
T38
T35
T32
T43
R477 *0_02
R416 49.9_1%_04
R491 *2.2K_04
T40
R401K_04
U21G
TGL_U_IP_EXT
SNDW_RCOMP
DF33
GPP_A10/I2S2_RXD/DMIC_DATA1
DG50
GPP_R1/HDA_SYNC/I2S0_SFRM
DU37
GPP_A23/I2S1_SCLK
DG41
GPP_S5/SNDW 2_DATA/DMIC_DATA1
DK31
GPP_S4/SNDW 2_CLK/DMIC_CLK_A1
DK33
GPP_A13/PMC_I2C_SCL/I2S3_TXD/DMIC_CLK_B0
DH49
GPP_S2/SNDW 1_CLK/DMIC_CLK_B0
DW35
GPP_S7/SNDW 3_DATA/DMIC_DATA0
DM31
GPP_S6/SNDW 3_CLK/DMIC_CLK_A0
DN31
GPP_S0/SNDW 0_CLK
DT32
GPP_A11/PMC_I2C_SDA/I2S3_SCLK
DL52
GPP_A8/I2S2_SFRM/CNV_RF_RESET#/DMIC_DATA_0
DG51
GPP_R4/HDA_RST#
DV41
GPP_R3/HDA_SDI0/I2S0_RXD
DV37
GPP_R5/HDA_SDI1/I2S1_RXD
DW38
GPP_A9/I2S2_TXD/MODEM_CLKREQ/CRF_XTAL_CLKREQ/DMIC_CLK_A1
DL49
GPP_D19/I2S_MCLK1
DW24
GPP_R7/I2S1_SFRM
DT38
GPP_F8/I2S_MCLK2_INOUT
DW15
GPP_R0/HDA_BCLK/I2S0_SCLK
DR38
GPP_A7/I2S2_SCLK/DMIC_CLK_A0
DL53
GPP_R2/HDA_SDO/I2S0_TXD
DT37
GPP_R6/I2S1_TXD
DV38
GPP_S1/SNDW 0_DATA
DR35
GPP_S3/SNDW 1_DATA/DMIC_CLK_B1
DV35
R37*1K_04
R49 *1K_04
T27
T30
T33
R492 *0_02
T6
T26
T8
T37
D38RB751S-40H
AC
T31
R44*1K_04
R536 1K_04
R29 10K_04
T44
T41
R436 2.2K_1%_04
R484 *0_02
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