R97 1K_04
C66 0.1u_10V_X7R_04
L56
HCB1005KF-121T20
C534
4.7u_6.3V_X5R_06
R1372K_04
L55
HCB1005KF-121T20
C195
1u_6.3V_X5R_04
R1382K_04
L68
HCB1005KF-121T20
R805
*15mil_short_06
.
L74
BCIHP0420TB-2R2M
C231
0.01u_16V_X7R_04
C270
0.1u_16V_Y5V_04
C438
4.7u_6.3V_X5R_06
C233
0.1u_16V_Y5V_04
R160 0_04
C169
1u_6.3V_X5R_04
U65
PS8625
SW_OUT
15
SW_OUT
16
GNDX
17
GNDX
18
VDD12
19
TESTMODE
20
RLV_LNK/GPIO0
21
RLV_CFG
22
ENBLT
23
CSDA/MSDA
24
CSCL/MSCL
25
REXT
26
BLV_AMP
27
GND
28
TA1n
42
TA1p
41
TB1n
40
TB1p
39
VDDIO
38
TC 1n
37
TC 1p
36
TCK1n
35
TCK1p
34
ENPVCC/I2C_ADDR
33
TD 1n
32
TD 1p
31
DDC_SDA
30
DDC_SCL
29
NC
56
NC
55
TA0n
54
TA0p
53
TB0n
52
TB0p
51
VDDIO
50
TC0n
49
TC0p
48
TCK0n
47
TCK0p
46
PWMI
45
TD0n
44
TD0p
43
DAUXn
1
DAUXp
2
GND
3
DRX0p
4
DRX0n
5
VDDRX
6
DRX1p
7
DRX1n
8
RST#
9
PD#
10
HPD
11
PWMO
12
VDDIOX
13
VDDIOX
14
Epad
57
D01a_1009_Alex
D01a_1009_Alex
C197
0.1u_16V_Y5V_04
R1274.99K_1%_04
R172 *0_04
R175 *4.7K_04
R155 0_04
R1324.99K_1%_04
C198
0.01u_16V_X7R_04
C51 0.1u_10V_X7R_04
R176 4.7K_04
C533
4.7u_6.3V_X5R_06
R177 4.7K_04
C200
0.1u_16V_Y5V_04
R13310K_04
R145 0_04
R178 *4.7K_04
C60 0.1u_10V_X7R_04
R147 0_04
R13610K_04
R125*4.7K_04
R149 0_04
C63 0.1u_10V_X7R_04
R126*4.7K_04
R174 *0_04
R154 0_04
C267
1u_6.3V_X5R_04
VDDI O
VDDIO
PS_BKL_EN 14
PWMO 14
LVDS_DDC_CLK 14
LVDS_DDC_DAT 14
LVDS_U0P 14
LVDS_U0N 14
PS_PANEL_EN 14
LVDS_U2P 14
LVDS_U1P 14
LVDS_U1N 14
LVDS_UCLKN 14
LVDS_UCLKP 14
LVDS_U2N 14
LVDS_L1P 14
LVDS_L0P 14
LVDS_L0N 14
LVDS_LCLKP 14
LVDS_L2N 14
LVDS_L2P 14
LVDS_L1N 14
iGP_eDP_AUX#_R14
iGP_eDP_AUX_R14
LVDS_LCLKN 14
BRIGHTNESS34
eDP_TX1_R14
eDP_TX#1_R14
iGP_eDP_HPD5,14
eDP_TX#0_R14
eDP_TX0_R14
EDP_DISP_UTIL5
3.3V 2,3,14,19,29,30,32,36,37,39,41,42,62
D01a_1009_Alex
DDC_SDA
DDC_SCL
D02 12/03 ValueÅܧó Gary
R121
100K_04
R115
*100K_04
PWMI
D02 12/03§ó·sValue Gary
D02_1116_Alex
D02 12/03 ValueÅܧó Gary
C170
0.47u_16V_Y5V_06
C2382.2u_16V_X5R_06
R150 0_04
R165 0_04
SMD_VGA_THERM13,34
SMC_VGA_THERM13,34
ENBLT
VDDIOX VDD12
ENPVCC
SW_OUT
PWMO
Initial Code EEPROM
GNDAGND
PGND
VDDIO
1. Place the switching regulator inductor (L3) close to SW_OUT Pins (Pin15, Pin16).
2 . Th e SW_OUT ou tput traces s hou ld be as wide as pos sible.
3. The GNDX pins (Pin17, Pin18) should be connected to the main PCB ground plane, with the device GND pins of the PS8625 connected to separate GND island (GNDA) for the device.
The GND island (GNDA) should be connected to the main GND plane (GND) with a single-point connection by use of a wide PCB trace.
4. Place the 4.7uF decoupling Capacitor (C4) for VDDIOX close to VDDIOX pin.
5. The GND of the 4.7uF capacitor (C4) for VDDIOX should be placed close to the GND of 4.7uF capacitor (C5) behind Inductor.
6 . Plac e the b ead (L 2) f or VD DIOX clos e to PS8 625 .
D02 12/03 ValueÅܧó Gary
D02 12/03 ValueÅܧó Gary
VDDI O
EC BRIGHTNESS
CPU EDP BRIGHTNESS
VDDI O
LVDS_UCLKN
LVDS_U2P
LVDS_U2N
LVDS_U1P
LVDS_U1N
LVDS_U0P
LVDS_U0N
LVDS_UCLKP
12/06 valueÅܧó Gary
TD0p
TD0n
LVDS_L2N
LVDS_L1P
LVDS_L1N
TD1p
TD1n
LVDS_L0P
LVDS_L0N
LVDS_LCLKP
LVDS_LCLKN
LVDS_L2P
Power On Configuration
D02 12/03 ValueÅܧó Gary
RLV_LNK: LVDS single link or dual link selection, internal pull-down ~80K
L: Single link LVDS
H: Dual link LVDS
LVDS_U1N
LVDS_U0P
LVDS_U0N
VDDIORLV_LNK/GPIO0
LVDS_UCLKP
LVDS_U2P
LVDS_U2N
LVDS_U1P
TD 1p
ENPVCC
LVDS_L0P
LVDS_L0N
3.3V
LVDS_L2P
PD#
LVDS_L1P
DRX0p
LVDS_L1N
DRX1p
VDDIO
RST#
DRX1n
DRX0n
VDDI OX
VDDI OX
PS_HPD
PD#
D01A_1016_Alex
Switching Regulator Layout Guideline
RST#
GNDA
LVDS_LCLKN
PWMO
LVDS_LCLKP
VDDIO
VDD12
SW_OUT
SW_OUT
LVDS_L2N
CSDA/MSDA
ENBLT
RLV_CFG
GND
GND
Noe:
R13: LVDS output swing control
4.99K f or default swing, change the v alue f or swing adjust
TD 1n
CSCL/MSCL
RLV_LNK/GPIO0
PWM I
TD0n
I2C_ADDR: I2C Slav e address selection, internal pull-down ~80K
L: 0x10h~0x1Fh
H: 0x90h~0x9Fh
VDDIOENPVCC
I2C_CFG = "H"
EEPROM for Initial Code
I2C Address: 0xA0
Suggest minimum 2Kbit
VDDIO
VDDRX
GNDA
RLV_AMP
RLV_LNK/GPIO0
Note:
The decoupling caps C9, C15, C16, C17, C18, C21
shall be close to the power pins as possible
CSCL/MSCL
CSDA/MSDA
singl e PCB trace
DAUXn
GNDA
DAUXp
VDDRX
D02 12/03 ValueÅܧó Gary
L_BRIGHTNESS_R22
DAUXn
R179 0_04
DRX1n
DRX1p
DRX0n
DRX0p
DAUXp
VDDIORLV_CFG
RLV_CFG: LVDS color depth and data mapping selection, internal pull-down ~80K
L: 8-bit LVDS, VESA mapping
M: 8-bit LVDS, JEIDA mapping
H: 6-bit LVDS, both VESA and JEIDA mapping
LVDS_UCLKN
GND
TD0p
3.3V
U77
*M24C02~M24C16
VCC
8
WC#
7
SCL
6
SDA
5
VSS
4
E2
3
E1
2
E0
1
PS_HPD
PS_REXT
D01A_1016_Alex
To Next Page
Loading...
