5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_TCK TERMINATION PLACE NEAR CPU WITHIN 1.1 INCH
CPU_24MHZ
SKYLAKE-S Processor 2/7 (JTAG,CLK,CFG ,DISPLAY)
CAD Note: Capacitor need to be placed
close to buffer output pin
PLACE INSIDE CPU CAVITY
Stall reset sequence after PCU PLL lock until de-asserted:
1 = (Default) Normal Operation;
No stall.
0 = Stall.
CFG TABLE
CFG[0]
CFG[1]
CFG[19:8]
Reserved configuration lane.
CFG[2]
PCI Express* Static x16 Lane Numbering Reversal.
1 = Normal operation
0 = Lane numbers reversed.
CFG[3]
Reserved configuration lane.
CFG[4]
eDP enable:
1 = Disabled.
0 = Enabled.
CFG[6:5]
PCI Express* Bifurcation
00 = 1 x8, 2 x4 PCI Express*
01 = reserved
10 = 2 x8 PCI Express*
11 = 1 x16 PCI Express*
CFG[7]
PEG Training:
1 = (default) PEG Train immediately following RESET# deassertion.
0 = PEG Wait for BIOS for training.
Reserved configuration lanes.
CFG6
CFG7
CFG0
CFG2
CFG4
CFG5
CFG_RCOMP
H_PRDY_N
H_PREQ_N
H_TRST_N
H_TCK
H_TMS
H_TDI
H_TDO
H_TRST_N
H_PREQ_N
H_TCK
H_PROCHOT_N H_PROCHOT_R_N
H_VIDSOUT
H_VIDSCK
CPU_VIDALERT_N
H_VIDALERT_N
H_VIDSOUT
H_PROCHOT_N
H_THRMTRIP#
DDR_VTT_CNTL
VCCST_PWRGD_CPU
H_PM_DOWN_R
H_THRMTRIP#
PECI
H_THERMTRIP_N
AUD_AZACPU_SDI_R
DP_RCOMP
H_PROCHOT_N
H_TDO
H_SKTOCC_N
CFG1
CFG3
BPM0
BPM1
BPM2
BPM3
VCCST_VCCPLL
VCCIO
VCCST_VCCPLL
3.3VA
PCH_CPU_BCLK_DP19
PCH_CPU_BCLK_DN19
PCH_CPU_PCIBCLK_DP19
PCH_CPU_PCIBCLK_DN19
PCH_CPU_NSSC_CLK_DP19
PCH_CPU_NSSC_CLK_DN19
H_PROCHOT_N49
H_VIDALERT_N_VR49
H_VIDSOUT_VR49
H_VIDSCK_VR49
H_PECI17,30
H_PWRGD18
PLTRST_CPU_N17
H_PM_DOWN17
H_THRMTRIP#17
H_PM_SYNC17
VCCST_VCCPLL5,18,46,49
3.3VA16,17,18,20,21,46
AUD_AZACPU_SDO_R 18
AUD_AZACPU_SCLK_R 18
AUD_AZACPU_SDI 18
VCCIO2,5,43
H_PROCHOT_EC30
VCCST_PWRGD17,21
DDR_VTT_CNTL44
H_SKTOCC_N19
Title
Size Document Number R e v
Date: Sheet
of
6-71-P77F0-D02
2.0
[03] Processor 2/5-CLK,MISC,DIS
A3
369Wednesday, October 25, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number R e v
Date: Sheet
of
6-71-P77F0-D02
2.0
[03] Processor 2/5-CLK,MISC,DIS
A3
369Wednesday, October 25, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
Title
Size Document Number R e v
Date: Sheet
of
6-71-P77F0-D02
2.0
[03] Processor 2/5-CLK,MISC,DIS
A3
369Wednesday, October 25, 2017
ᙔ!Ϻ!ႝ!တ!!DMFWP!DP/
SCHEMATIC1
R579 2.74K_1%_04
R91 *20mil_04
R572 1K_1%_04
R549 *51_04
R64
100K_04
R550 51_04
R555 *20mil_04
R578 20_1%_04
R557 56.2_1%_04
R92 24.9_1%_04
R552 20_1%_04
R554 220_04
R580 6.04K_1%_04
R553 *20mil_04
R548 499_1%_04
R547 1K_1%_04
R558 *20mil_04
SKL_S_CPU
LGA1151
5 OF 12
?
?REV = 1.2
U39E
SKL_S_CPU_LGA
PCI_BCLKP
W1
VIDSCK
E38
CATERR#
D13
PROC_SELECT#
AB36
SKTOCC#
AB35
ZVM#
AC38
DDR_VTT_CNTL
AC36
VIDSOUT
E40
CLK24P
K9
CLK24N
J9
CFG_RCOMP
M11
PROC_PRDY#
B10
PROC_PREQ#
B9
PROC_TRST#
F12
PROC_TCK
F11
PROC_TMS
F13
PROC_TDI
G12
PROC_TDO
H13
BPM#[3]
H14
BPM#[2]
G14
BPM#[1]
D17
BPM#[0]
D16
CFG[18]
G18
CFG[17]
F14
CFG[15]
H19
CFG[14]
F21
CFG[13]
F20
CFG[12]
G20
CFG[11]
H17
CFG[10]
F17
CFG[9]
E16
CFG[8]
G16
CFG[7]
H20
CFG[5]
H18
CFG[6]
G21
CFG[4]
F19
CFG[3]
H16
CFG[2]
F16
CFG[1]
F15
CFG[0]
H15
PCI_BCLKN
W2
BCLKN
W4
BCLKP
W5
THERMTRIP#
D11
PECI
G7
PM_DOWN
D8
PM_SYNC
E8
RESET#
E7
PROCPWRGD
F8
PROCHOT#
C39
VCCST_PWRGD
U2
RSVD_AC37
AC37
CFG[19]
F18
CFG[16]
E14
VIDALERT#
E39
R551 51_04
R556 100_1%_04
R86 *20mil_04
Q8
2SK3018S3
G
DS
LGA1151
SKL_S_CPU
?
4 OF 12
?REV = 1.2
U39D
SKL_S_CPU_LGA
DDI1_TXN[3]
D23
EDP_TXN[1]
C9
EDP_TXN[2]
H10
EDP_TXP[2]
G10
DDI1_TXN[1]
E22
DDI1_TXP[1]
D22
DDI1_TXN[0]
D21
DDI1_TXP[2]
B23
DDI1_TXN[2]
A23
DDI1_TXP[3]
C23
DDI1_TXP[0]
C21
EDP_TXP[0]
E10
EDP_TXN[0]
D10
EDP_TXP[1]
D9
EDP_TXN[3]
G9
EDP_TXP[3]
F9
EDP_AUXP
D12
EDP_AUXN
E12
EDP_DISP_UTIL
D14
EDP_RCOMP
M9
PROC_AUDIO_CLK
V3
PROC_AUDIO_SDI
V2
PROC_AUDIO_SDO
U1
DDI1_AUXP
B13
DDI2_TXN[2]
D19
DDI2_TXP[3]
D20
DDI2_TXP[2]
C19
DDI2_TXN[1]
E18
DDI2_TXP[1]
D18
DDI2_TXN[0]
A18
DDI2_TXP[0]
B18
DDI1_AUXN
C13
DDI2_TXN[3]
E20
DDI2_AUXN
B12
DDI2_AUXP
A12
DDI3_TXP[0]
B14
DDI3_TXN[0]
A14
DDI3_TXP[1]
C15
DDI3_TXN[1]
B15
DDI3_TXP[2]
B16
DDI3_TXN[2]
A16
DDI3_TXP[3]
C17
DDI3_TXN[3]
B17
DDI3_AUXN
C11
DDI3_AUXP
B11
R568 *51_04
R573 49.9_1%_04
R157 10K_04
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