Clevo W150ERQ - Sequence

RTCRST#
VCCRTC
5V
3V
PWRBTN#
SLP_S3#
SLP_S4#
DD_ON#
1.5VS
APWROK
1.05VS
PWROK
H_VTTPWRGD(ALL_SYS_PWRGD)
IMVP_VR_EN
CPU SVID BUS
1.8VS(VccPLL)
SPEC MIN 9mS
SPEC MIN 99mS
SPEC MAX 90mS
SPEC MIN 10mS
setVID
SLOW
packet
SPEC MIN 30uS
SPEC MIN 30us
SUS_STATE#
PLT_RST#
PB50/PB70 Huron River POWER SEQUENCE
81.24mS
1.3mS
420uS
91.073mS
31.6mS
734mS
SUS_PWR_DN_ACK 240mS
SPEC MAX 200mS
36.47uS
122mS
SPEC Minimum duration of PWRBTN# assertion = 16mS.
PWRBTN# can assert before or after RSMRST#
1.307mS
1.5V
195.3mS
149.4mS
12.3mS
10.5mS
11.5mS
1.785mS
2.0mS
8.7mS
2.35mS
2.15mS
1.8mS
1.2mS
Will never go high later than SLP_S3#SPEC MIN 5msSLP_A#
SPEC MIN 0ms
SPEC MIN 5mS
SLP_S5#
0.85VS
1.05VS_VTT
SPEC MIN 1ms
SPEC MIN 0ms
3.3VS
5VS
SPEC MIN 0mS
DRAMPWROK
SPEC MIN 2mS~MAX650ms
SPEC MIN 1mSSYS_PWROK
SPEC MIN 1mS~MAX100ms
SPEC MIN 60uS
SPEC MAX500us
SPEC MIN MAX5ms
A
C
K
SPEC MAX50us
SPEC MIN50us~MAX2000us
VCORE
SPEC MAX5ms
ACPRESENT
RSMRST#
2.17mS
5mS
36mS
MVP_PWRGD (VR_Ready)
IMVP_VR_EN
UNCOREPWRGOOD
SPEC MIN 2mS
1.73mS
SPEC MIN 5mS~MAX650ms
Sheet 51 of 51
Sequence
Schematic Diagrams
B - 52 Sequence
B.Schematic Diagrams
Sequence