CLK_DP_P 21
CLK_DP_N 21
H_PROCHOT#42,44
H_THRMTRIP#25
H_PECI21,25,36
H_PM_SYNC22
3.3VS9,10, 11,20,21,22,23,24,25,26,27,29,30,32,33,34,35,36,37,42,44
PL T_R ST#24,30
H_CPUPWRGD25
DDR3_DRAMRST# 9,10
DRAMRST_CNTRL 6,21
H_SNB_IVB#25
H_PROCHOT#_EC36
SUSB37,39,40,41
1.8VS_PWRGD22,39
PM_DRAM_PWRGD22
1.5V6,9,10,27, 37,40
H_PROCHOT#
H_CPUPWRGD_R
S3 circuit:- DRAM PWR GOOD logic
CAD N ote: Capacitor need to be placed
close to buffer output pin
TRACE WIDTH 10MIL, LENGTH <500MILS
H_CPUPWRGD_R
Processor Pullups/Pull downs
H_PROCHOT#
BUF_CPU_RST#
H_CATERR#
XD P _ D B R _ R
XDP _TD I_R
SM_RCOMP_2
SM_RCOMP_1
SM_RCOMP_0
XDP_TRST#
XD P _ TC L K
VDDPWRGOOD_R
H_PROCHOT#_D
XD P _ TM S
H_PROCHOT#
CPUDRAMRST#
XDP_PR EQ#
XD P _ TD I _ R
XD P _ TD O _ R
R31 *10mil_short
R50 *10mil_short
If PROCHOT# is not used,
then it must be terminated
with a 56-£[ +-5% pull-up
resistor to 1.05VS_VTT .
DDR3 Compensation Signals
BUF_CPU_RST#
SM_RCOMP_1
SM_RCOMP_0
SM_RCOMP_2
XDP_PR DY#
PMSY S_PWRGD_BUF
2011.10.25
Ivy Bridge Processor 2/7 ( CLK,MISC,JTAG )
Buffered reset to CPU
CPUDRAMRST#
S3 circuit:- DRAM_RST# to memory
should be high during S3
R45
*39_04
R306 *0_04
C132
47p_50V_NPO_04
R35
75_04
R51
100K_04
R304
1K_04
R49 62_04
Q4
*MTN7002ZHS3
G
DS
R25 1K_04
S
D
G
Q2B
MTDN7002ZHS6R
5
34
R32 *10mil_short
R28
*750_1%_04
R36 43.2_1%_04
R33 10K_04
R57
*200_04
S
D
G
Q2A
MTDN7002ZHS6R
2
61
R37 *1.5K_1%_04
R58
*100K_04
Q3
MTN7002ZHS3
G
DS
R46 56_1%_04
RN11 56_8P4R_04
1
2
3
45
6
7
8
R318 200_1%_04
R48 130_1%_04
R34
10K_04
C515
0.047u_10V_X7R_04
XDP _TD O_R
XD P _ D B R _ R
R38
200_1%_04
PU/PD for JTAG signals
XD P _ TR S T#
XDP_PR EQ#
XDP _TC LK
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
U17B
PZ98821-364B-01F
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_DRAMRST#
R8
SM_RCOMP[0]
AK1
BCLK#
A27
BCLK
A28
DPLL_REF_CLK#
A15
DPLL_REF_CLK
A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
TH ERMTR IP #
AN32
SM_DRAMPW ROK
V8
RESET#
AR33
PRDY#
AP29
PREQ#
AP27
TC K
AR26
TMS
AR27
TRST#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
R305 1K_04
R18 140_1%_04
Q22
MTN7002ZHS3
G
DS
C134
68p_50V_NPO_04
R317 25.5_1%_04
C137
*0.1u_16V_Y5V_04
PMSYS_PWRGD_BUF
R325*51_04
R319
4.99K_1%_04
R32851_04
U5
*MC74VHC1G08DFT1G
1
2
5
4
3
R44
100K_04
3.3VS
1.5V
1.05VS_VTT
3.3V
1.5VS_CPU
3.3V
XDP _TMS
1.05VS_VTT
1.05VS_VTT
1.05VS_VTT2,5,25,26,27,37
3.3VS
CLK_EXP_N 21
CLK_EXP_P 21
1.5VS_CPU6,37,40
3.3V2,6,11,18,20,21,22,24,25,26,27,29,30,31,35,37,39,40,41
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