Cmsemicon SC8F577 Series - Page 73

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9.3 TIMER2 related register
There are 2 registers related to TIMER2, namely data memory TMR2 and control register T2CON.
TIMER2 data register TMR2 (11H)
11H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TMR2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
X
X
X
X
X
X
X
X
TIMER2 control register T2CON (12H)
12H
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
T2CON
CLK_SEL
TOUTPS3
TOUTPS2
TOUTPS1
TOUTPS0
TMR2ON
T2CKPS1
T2CKPS0
Read write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset value
0
0
0
0
0
0
0
0
Bit7
CLK_SEL:
Choice of clock source
1=
External 32.768kHz /4 as TMR2 clock source (can continue to count in sleep
state);
0=
Internal F
CPU
as TMR2 clock source
Bit6~Bit3
TOUTPS<3:0>:
TIMER2 output frequency division ratio selection bit.
0000=
1:1;
0001=
1:2;
0010=
1:3;
0011=
1:4;
0100=
1:5;
0101=
1:6;
0110=
1:7;
0111=
1:8;
1000=
1:9;
1001=
1:10;
1010=
1:11;
1011=
1:12;
1100=
1:13;
1101=
1:14;
1110=
1:15;
1111=
1:16.
Bit2
TMR2ON:
TIMER2 enable bit;
1=
Enable TIMER2;
0=
Disable TIMER2.
Bit1~Bit0
T2CKPS<1:0>:
TIMER2 clock frequency division ratio selection bit;
00=
1;
01=
4;
1x=
16.