GR712RC-QSG
November 2018, Version 1.0
21 www.cobham.com/gaisler
5. Frequently Asked Questions / Common Mistakes / Know Issues
5.1. Clock gating
Several of the design's peripherals may be clock gated off. GRMON will enable all clocks if started with the flag
-cginit. Within GRMON, the command grcg enable all will have the same effect.
Alternatively, if a boot loader is used instead of GRMON to load an executable, then clock gating must be setup
via the General Purpose register. Clock source/divider selection must also be setup for the MIL-1553, SpaceWire
and TM cores. See Chapter 13 of [RD-2].
5.2. GRMON issues
When connected to the board, the message "stack pointer not set" will be shown by the command info sys in case
GRMON doesn't find any memory.
5.3. Clock problems
Ensure that the jumper JP84, selecting the clock source, is always present. A combination of its absence and the
presence of jumper JP88, can lead to unexpected processor behavior.
When jumper JP88 is present, the oscillator in socket X5, which is provided by default, must be disconnected or
it will short with the main clock source, leading to possible damage to the oscillators and unexpected behavior.
5.4. Switch Matrix Configuration Problems
Ensure that the jumper array is properly configured and that any I/O peripheral required is clock ungated or enabled.
The internal switch matrix routing is explained more in depth in Chapter 2 of GR712RC User Manual.
If an IP core behaves correctly, as seen from software, but does not receive/transmit any data from the outside,
first check that the jumper array is properly configured. The problem might also arise when conflicting cores are
enabled. Check Table 8 from [RD-2] for further information on conflicting cores.
5.5. GPIO
Some of the GPIOs have special meaning on power-up, GPIO[1] and GPIO[3] configure the PROM area of the
memory controller and GPIO[42], GPIO[40], GPIO[37] and GPIO[34] are used for the SPW clock divider reset
value.
These pins are provided with pull-down resistors by default. If measuring the state of these GPIO pins, please take
into account the effect of these pull-down resistors. Conversely, if an external signal is connected to the GPIO[3]
and GPIO[1] pins, this may override the expected state of the pin at power up.
See Section 2.3.2 and Section 2.6.2 of [RD-1] for more information.
5.6. SDRAM configuration
SDRAM is, by default, not configured on the board. Ensure that the switch matrix jumper configuration is correctly
set as to enable SDRAM. If in doubt, you can use a default configuration that supports SDRAM. See Section 2.3
for more details.
Only half of the installed SDRAM will be available in the system, as reported by GRMON's info sys command.
This limitation is due to the fact that the SODIMM provides 64 bit data paths, but in the standard LEON model
only 32 bits of the SDRAM are used, plus 16 additional data bits for the RS/EDAC memory bits.
5.7. Multiprocessor & legacy support
Code compiled for the single core LEON3 will generally be able to run unmodified on the GR712RC. The second
core is inactivated after reset and unless it's activated (by writing a specific bit in the IRQ controller) it will remain
inactivated and the chip will behave as a single-CPU system.
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