COBHAM GR740 User Manual

GR740
Quad Core LEON4 SPARC V8 Processor
2017 Preliminary Data Sheet and User’s Manual
The most important thing we build is trust
GR740-UM-DS, Nov 2017, Version 1.7 www.cobham.com/gaisler
Features
• Fault-tolerant quad-processor
SPARC V8 integer unit
with 7-stage pipeline, 8 register windows, 4x4 KiB
instruction and 4x4 KiB data caches.
• Double-precision IEEE-754 floating point units
• 2 MiB Level-2 cache
• 64-bit PC100 SDRAM memory interface with Reed-
Solomon EDAC*
• 8/16-bit PROM/IO interface with EDAC*
• SpaceWire router with eight SpaceWire links
• 2x 10/100/1000 Mbit Ethernet interfaces*
• PCI Initiator/Target interface*
• MIL-STD-1553B interface*
• 2x CAN 2.0 controller interface*
• 2x UART, SPI, Timers and watchdog, 16+22 GPIO*
• CPU and I/O memory management units
• SpaceWire Time Distribution Protocol controller and
support for time synchronisation
• JTAG, Ethernet* and SpaceWire* debug links
* Interfaces have shared pins
Description
The GR740 device is a radiation-hard system-on-
chip featuring a quad-core fault-tolerant LEON4
SPARC V8 processor, eight port SpaceWire router,
PCI initiator/target interface, MIL-STD-1553B
interface, CAN 2.0 interfaces and 10/100/1000
Mbit Ethernet interfaces.
Specification
• System frequency: 250 MHz
• Main memory interface: PC100 SDRAM
• SpaceWire router with SpaceWire links: 300
Mbit/s
• 33 MHz PCI 2.3 initiator/target 
interface
• Ethernet 10/100/1000 Mbit MACs
• CCGA625 / LGA625 package
Applications
The GR740 device is targeted at high-performance general purpose 
processing. The architecture is suitable for both symmetric and 
asymmetric multiprocessing. Shared resources can be monitored to 
support mixed-criticality applications.
FPU
MMU
Caches
X
LEON4 LEON4
FPUFPU
MMU
Caches
Ethernet
MIL-STD
1553B
CAN
Controller
SpW router
PCI
Target
PCI
DMA
Bootstrap
GP register
TDP
controller
SPI
controller
Timer unit 0
watchdog
GPIO port
0 - 1
UART
Temperature
sensor
Clock gating
unit
Pad / PLL
controller
AHB
Status
Timer units
1 - 4
PCI
Master
L2
Cache
SDRAM
CTRL w.
EDAC
Memory
Scrubber
PROM
& IO
CTRL w.
EDAC
AHB/APB
Bridges
AHB/AHB
Bridge
AHB Bridge
IOMMU
AHB
Status
AHB/AHB
Bridge
DSU4
AHB/APB
Bridge
SpW RMAP
DCL
AHBTRACE
JTAG
DCL
IRQ(A)MP
LEON4
STAT.UNIT
Debug bus
32-bit APB
SSS
SM
MSS
32-bit APB
MS
M
S
X
MM MM
SSSSSS
M
S
MM
S
S
S
X
M
M
S
MM
M
SSS
S
MXMXMXMX
Processor bus
128-bit AHB
Memory bus
128-bit AHB
SM
X
SSSSSS
S
S
Slave IO bus
32-bit AHB
S
S
S
S
S
S
Statistics
SS
96-bit
PC100
SDRAM
PROM
IO
8/16-bit
32-bit AHB
Master IO bus
32-bit AHB
MMU
Caches

COBHAM GR740 Specifications

General

Brand	COBHAM
Model	GR740
Category	Computer Hardware
Language	English

Summary

2 Architecture

2.3 Memory map

Details the memory map of internal AHB and APB buses as seen from processor cores.

6 LEON4 - Fault-tolerant High-performance SPARC V8 32-bit Processor

6.1 Overview

Introduces the LEON4 processor core, its architecture, and features.

6.2 LEON4 integer unit

Details the integer unit implementation, pipeline, and features.

13 SpaceWire router

13.1 Overview

Introduces the SpaceWire router, its RMAP target, and port types.

14 Gigabit Ethernet Media Access Controller (MAC)

14.1 Overview

Introduces the GRETH_GBIT interface between AMBA-AHB and Ethernet.

15 32-bit PCI/AHB bridge

15.1 Overview

Describes the GRPCI2 core as a bridge between PCI and AMBA AHB buses.

16 MIL-STD-1553B / AS15531 Interface

16.1 Overview

Introduces the interface core connecting AHB/APB to MIL-STD-1553B bus.

17 CAN 2.0 Controllers with DMA

17.1 Overview

Introduces two CAN controllers supporting DMA for message transfer.

21 Multiprocessor Interrupt Controller with extended ASMP support

21.1 Overview

33 LEON4 Hardware Debug Support Unit

33.1 Overview

Introduces the DSU for simplifying debugging on target hardware.

33.2 Operation

35 SpaceWire Debug Link

35.1 Overview

36 AHB Trace buffer tracing Master I/O AHB bus

36.1 Overview

43 Silicon Revisions and Errata

43.1 Overview

Lists design changes and errata based on silicon revision.

43.2 Change and errata descriptions

Details specific changes and errata descriptions for LEON4, Ethernet, PCI, and SDRAM controller.