GR740-UM-DS, Nov 2017, Version 1.7 60 www.cobham.com/gaisler
GR740
Because the cache is virtually tagged, no extra clock cycles are needed in case of a cache load or
instruction cache hit. In case of miss or write buffer processing, a translation is required which might
add extra latency to the processing time, depending on if there is a TLB miss. TLB lookup is done at
the same time as tag lookup and therefore add no extra clock cycles.
If there is a TLB miss the page table must be traversed, resulting in up to four AMBA read accesses
and one possible writeback operation. See the SRMMU specification for the exact format of the page
table.
An MMU page fault will generate trap 0x09 for the D-cache and trap 0x01 for the I cache, and update
the MMU status registers according to table 40 and the SRMMU specification. In case of multiple
errors, they fault type values are prioritized as the SRMMU specification requires. The cache and
memory will not be modified on an MMU page fault.
6.4.3 Translation look-aside buffer (TLB)
The MMU has separate TLBs for instructions and data. The number of TLB entries (for each imple-
mented TLB) is 16. The organisation of the TLB and number of entries is not visible to the software
and does thus not require any modification to the operating system. The TLB can be flushed using an
STA instruction to ASI 0x18, see section 6.9.6.
6.5 Floating-point unit
The high-performance GRFPU operates on single- and double-precision operands, and implements all
SPARC V8 FPU operations including square root and division. The FPU is interfaced to the LEON4
pipeline using a LEON4-specific FPU controller (GRFPC) that allows FPU instructions to be exe-
cuted simultaneously with integer instructions. Only in case of a data or resource dependency is the
integer pipeline held. The GRFPU is fully pipelined and allows the start of one instruction each clock
cycle, with the exception is FDIV and FSQRT which can only be executed one at a time. The FDIV
and FSQRT are however executed in a separate divide unit and do not block the FPU from performing
all other operations in parallel.
All instructions except FDIV and FSQRT has a latency of three cycles, but to improve timing, the
LEON4 FPU controller inserts an extra pipeline stage in the result forwarding path. This results in a
Table 40. LEON4 MMU Fault Status Register, fault type values
Fault type SPARC V8 ref Priority Condition
6 Internal error 1 Never issued by LEON SRMMU
4 Translation error 2 AHB error response while performing table walk. Transla-
tions errors as defined in SPARC V8 manual. A translation
error caused by an AMBA ERROR response will over-
write all other errors. Other translation errors do no over-
write existing translation errors when FAV = 1.
1 Invalid address error 3 Page table entry for address was marked invalid
3 Privilege violation
error
4 Access denied based on page table and su status (see
SRMMU spec for how privilege and protection error are
prioritized)
2 Protection error 5
0 None - No error (inside trap this means the trap occurred when
fetching the actual data)
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