GR740-UM-DS, Nov 2017, Version 1.7 2 www.cobham.com/gaisler
GR740
Table of contents
1 Introduction.............................................................................................................................. 8
1.1 Scope ....................................................................................................................................................... 8
1.2 Preliminary data sheet limitations ...........................................................................................................8
1.3 Updates and feedback.............................................................................................................................. 8
1.4 Software support...................................................................................................................................... 8
1.5 Development board ................................................................................................................................. 8
1.6 Performance, power consumption and radiation tolerance ..................................................................... 8
1.7 Reference documents .............................................................................................................................. 9
1.8 Document revision history .................................................................................................................... 10
1.9 Acronyms .............................................................................................................................................. 13
1.10 Definitions ............................................................................................................................................. 14
1.11 Register descriptions ............................................................................................................................. 15
2 Architecture............................................................................................................................ 16
2.1 Overview ............................................................................................................................................... 16
2.2 Cores...................................................................................................................................................... 18
2.3 Memory map ......................................................................................................................................... 19
2.4 Interrupts ............................................................................................................................................... 22
2.5 Plug & play and bus index information................................................................................................. 22
3 Signals.................................................................................................................................... 27
3.1 Bootstrap signals ................................................................................................................................... 27
3.2 Configuration for flight ......................................................................................................................... 28
3.3 Pin multiplexing .................................................................................................................................... 28
3.4 Complete signal list ............................................................................................................................... 32
3.5 Pin driver configuration......................................................................................................................... 35
4 Clocking and reset.................................................................................................................. 36
4.1 Clock inputs........................................................................................................................................... 36
4.2 Clock loop for SDRAM ........................................................................................................................ 36
4.3 Reset scheme ......................................................................................................................................... 37
4.4 Clock multiplexing for main system clock, SDRAM and SpaceWire .................................................. 38
4.5 PLL control and configuration .............................................................................................................. 39
4.6 PLL watchdog ....................................................................................................................................... 40
4.7 PCI clock ............................................................................................................................................... 40
4.8 MIL-STD-1553B clock ......................................................................................................................... 40
4.9 Clock gating unit ...................................................................................................................................40
4.10 Debug AHB bus clocking...................................................................................................................... 41
4.11 Notes on Ethernet interface clock and mode switch ............................................................................. 41
5 Technical notes....................................................................................................................... 42
5.1 GRLIB AMBA plug&play scanning ..................................................................................................... 42
5.2 Processor register file initialisation and data scrubbing........................................................................ 42
5.3 PROM-less systems and SpaceWire RMAP .........................................................................................42
5.4 System integrity and debug communication links ................................................................................ 43
5.5 Separation and ASMP configurations ................................................................................................... 43
5.6 Clock gating .......................................................................................................................................... 44
5.7 Software portability............................................................................................................................... 45
5.8 Level-2 cache ........................................................................................................................................ 45
5.9 Time synchronisation ............................................................................................................................ 46
5.10 Bridges, posted-writes and ERROR response propagation................................................................... 47
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