GR740-UM-DS, Nov 2017, Version 1.7 344 www.cobham.com/gaisler
GR740
Note that IDs 0x39 (LOAD instructions) and 0x3A (STORE instructions) will both count all LDST
and SWAP instructions. The sum of events counted for 0x39 and 0x3A may therefore be larger than
the number of events counted with ID 0x38 (LOAD and STORE instructions).
The documentation for the Debug Support Unit contains more information on events 0x40 - 0x5F, see
section 33.3.2. Please note that the statistical outputs from the DSU may be subject to AHB trace buf-
fer filters. The same applies to events 0x70 to 0x7F that come from the AHBTRACE standalone AHB
trace buffer.
Collecting statistics on interrupt latency is possible using the interrupt timestamping mechnism
described in section 21.2.6. Interrupt latency can not be measured with the LEON4 statistics unit.
Master indexes are listed in section 2.5.
26.2 Multiple APB interfaces
The core has two AMBA APB interfaces, the first is connected via the Processor AHB bus and the
second is connected via the Debug AHB bus. The first APB interface always has precedence when
both interfaces handle write operations to the same address.
0x80 - 0x8F Active when master selected by CPU/AHBM field has request asserted while grant is
asserted for the master correspoding to the least significant nibble of the event ID.
The following map is a map between least siginificant nibble of this event and CPU/AHBM
field to masters in the system
8:6 - Masters 2, 1, 0 on memory AHB bus
5:0 - Masters on Processor AHB bus
0x90 - 0x9F Active when master selected by CPU/AHBM field has request asserted while grant is deas-
serted for the master correspoding to the least significant nibble of the event ID. See events
0x80 - 0x8F for a description of masters corresponding to the different events.
Table 435.Event types and IDs
ID Event description
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