GR740-UM-DS, Nov 2017, Version 1.7 16 www.cobham.com/gaisler
GR740
2 Architecture
2.1 Overview
The system is built around five AMBA AHB buses; one 128-bit Processor AHB bus, one 128-bit
Memory AHB bus, two 32-bit I/O AHB buses and one 32-bit Debug AHB bus. The Processor AHB
bus houses four LEON4FT processor cores connected to a shared L2 cache. The Memory AHB bus is
located between the L2 cache and the main external memory interface (SDRAM) and attaches a mem-
ory scrubber.
The two separate I/O AHB buses connect peripherals. Slave interfaces of the PCI master/target and
PROM/IO memory controller are placed on one bus (Slave I/O AHB bus). All master/DMA interfaces
are placed on the other bus (Master I/O AHB bus). The Master I/O AHB bus connects to the Processor
AHB bus via an AHB/AHB bridge that provides access restriction and address translation (IOMMU)
functionality. The IOMMU also has an AHB master interface connected to the Memory AHB bus.
The AHB master interface to use when propagating traffic from a peripheral on the Master I/O AHB
bus is dynamically configurable.
Peripheral unit register interfaces such as timers, interrupt controllers, UARTs, general purpose I/O
port, SPI controller, MIL-STD-1553B interface, Ethernet MACs, CAN controllers, and SpaceWire
router AMBA interfaces are connected via two AHB/APB bridges that are attached to the Processor
AHB bus.
The fifth bus, a dedicated 32-bit Debug AHB bus, connects a debug support unit (DSU), one AHB
trace buffer monitoring the Master I/O AHB bus and several debug communication links. The Debug
AHB bus allows for non-intrusive debugging through the DSU and direct access to the complete sys-
tem, as the Debug AHB bus is not placed behind an AHB bridge with access restriction functionality.
The chapters in this document have been grouped after the bus topology. The first chapters describe
components connected to the Processor AHB bus, followed by the Memory AHB bus, Master I/O
AHB bus and finally Slave I/O AHB bus, APB buses and Debug AHB bus.
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