GR740-UM-DS, Nov 2017, Version 1.7 317 www.cobham.com/gaisler
GR740
22.3 Registers
The core is programmed through registers mapped into APB address space.
Table 400. General Purpose I/O Port registers
APB address offset Register
0x00 I/O port data register
0x04 I/O port output register
0x08 I/O port direction register
0x0C Interrupt mask register
0x10 Interrupt polarity register
0x14 Interrupt edge register
0x18 Reserved
0x1C Capability register
0x20 Interrupt map register 0
0x24 Interrupt map register 1
0x28 Interrupt map register 2
0x2C Interrupt map register 3
0x30 - 0x3C Reserved
0x40 Interrupt available register
0x44 Interrupt flag register
0x48 Reserved
0x4C Pulse register
0x50 Reserved
0x54 I/O port output register, logical-OR
0x58 I/O port direction register, logical-OR
0x5C Interrupt mask register, logical-OR
0x60 Reserved
0x64 I/O port output register, logical-AND
0x68 I/O port direction register, logical-AND
0x6C Interrupt mask register, logical-AND
0x70 Reserved
0x74 I/O port output register, logical-XOR
0x78 I/O port direction register, logical-XOR
0x7C Interrupt mask register, logical-XOR
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