GR740-UM-DS, Nov 2017, Version 1.7 22 www.cobham.com/gaisler
GR740
2.4 Interrupts
The table below indicates the interrupt assignments. Note that the table below describes interrupt bus
lines, these can be remapped in the interrupt controller.
2.5 Plug & play and bus index information
The format of GRLIB AMBA Plug&play information is given in sections 37 and 38. The address
ranges of the plug&play configuration areas are given in the preceding section and is also replicated
Table 9. Interrupt assignments
Interrupt Peripheral Comment
1 GPTIMER0 GPTIMER unit 0, timer 1
2 GPTIMER0 GPTIMER unit 0, timer 2
3 GPTIMER0 GPTIMER unit 0, timer 3
4 GPTIMER0 GPTIMER unit 0, timer 4
5 GPTIMER0 GPTIMER unit 0, timer 5
6 GPTIMER1 Shared interrupt for all timers on GPTIMER unit 1
7 GPTIMER2 Shared interrupt for all timers on GPTIMER unit 2
8 GPTIMER3 Shared interrupt for all timers on GPTIMER unit 3
9 GPTIMER4 Shared interrupt for all timers on GPTIMER unit 4
10 IRQ(A)MP Extended interrupt line.
11 GRPCI/PCIDMA PCI master/target and PCI DMA
12 Unassigned Suitable for use by software for inter-processor and
inter-process synchronization.
13 Unassigned
14 Unassigned
15 Unassigned Note: Not maskable by processor
16 GRGPIO0 /1 / CAN The GPIO port has configuration registers that deter-
mine the mapping between general purpose I/O lines
and the four interrupt lines allocated to the GPIO port.
Interrupt lines 16 -18 are shared between the GPIO port
and CAN controllers.
Interrupt line 19 is shared between the GPIO port and
the SPI controller.
17 GRGPIO0 /1 / CAN
18 GRGPIO0 /1 / CAN
19 GRGPIO0/1/ SPICTRL
20 SPWROUTER AMBA I/F 0 SpaceWire router AMBA interface 0
21 SPWROUTER AMBA I/F 1 SpaceWire router AMBA interface 1
22 SPWROUTER AMBA I/F 2 SpaceWire router AMBA interface 2
23 SPWROUTER AMBA I/F 3 SpaceWire router AMBA interface 3
24 GRETH_GBIT0 Gigabit Ethernet MAC 0
25 GRETH_GBIT1 Gigabit Ethernet MAC 1
26 GR1553B MIL-STD-1553B interface controller
27 AHBSTAT/ST65THSENS Shared by all AHB Status registers in design and by
temperature sensor.
28 MEMSCRUB/L2CACHE Memory scrubber and L2 cache
29 APBUART0 UART 0
30 APBUART1 UART 1
31 GRIOMMU / GRSPWTDP /
SPWROUTER
IOMMU register interface interrupt.
CCSDS TDP controller interrupt
SpaceWire router AMBA configuration port interrupt
(only applies to silicon revision 1)