GR740-UM-DS, Nov 2017, Version 1.7 69 www.cobham.com/gaisler
GR740
6.10 Configuration registers
6.10.1 PSR, WIM, TBR registers
The %psr, %wim, %tbr registers are implemented as required by the SPARC V8 standard.
Table 46. %psr- Processor state register
31 28 27 24 23 20 19 14 13 12 11 8 7 6 5 4 0
IMPL VER ICC RESERVED EC EF PIL S PS ET CWP
0b1111 0b0011 0 0b000000 0 0 0x0 1 1 0 0b00000
rrr rrrwrwrwrwrwrw
31: 28 Implementation ID (IMPL), read-only hardwired to “1111” (15)
27: 24 Implementation version (VER), read-only hardwired to “0011” (3) for LEON3/LEON4.
23: 20 Integer condition codes (ICC), see sparcv8 for details
19: 14 Reserved
13 Enable coprocessor (EC) - read-only
12 Enable floating-point (EF)
11 8 Processor interrupt level (PIL) - controls the lowest IRQ number that can generate a trap
7 Supervisor (S)
6 Previous supervisor (PS), see SPARC V8 manual for details
5: Enable traps (ET)
4: 0 Current window pointer (CWP)
Table 47. %wim - Window Invalid Mask
31 87 0
RESERVED WIM
0NR
rrw
31: 8 RESERVED
7: 0 Window Invalid Mask (WIM)
Table 48. %tbr - Trap Base Register
31 12 11 4 3 0
TBA TT R
Taken from interrupt controller. Default is 0xC0000 0 0
rw r r
31: 12 Trap base address (TBA) - Top 20 bits used for trap table address
11: 4 Trap type (TT) - Last taken trap type.
3: 0 RESERVED
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