GR740-UM-DS, Nov 2017, Version 1.7 293 www.cobham.com/gaisler
GR740
The memory controller has been implemented with a bus ready timeout counter. The counter value
and counter reload value are available in MCFG7. The counter will be reloaded whenever the bus
ready signal is low (asserted). If the reload value is nonzero, then the counter will decrement with one
each clock cycle the core is waiting for bus ready to be asserted. If the counter reaches zero, the action
taken depends on the state of Bus Error Enable (BEXCN) in MCFG1. If BEXCN is ‘1’, then an
AMBA ERROR response will be generated and the counter will be reloaded (see section 5.10 for
information on ERROR response propagation). If BEXCN is ‘0’, then the bus ready enable for the
accessed memory area will be disabled and the core will ignore bus ready for the accessed area.
Bus ready timeout functionality is disabled when the bus ready counter reload value is zero
(MCFG7.BRDYCNTRLD = 0).
19.9 Registers
The core is programmed through registers mapped into APB address space.
Table 364.FTMCTRL memory controller registers
APB Address offset Register
0x00 Memory configuration register 1 (MCFG1)
0x04 RESERVED
0x08 Memory configuration register 3 (MCFG3).
0x0C RESERVED
0x10 Memory configuration register 5 (MCFG5).
0x14 RESERVED
0x18 Memory configuration register 7 (MCFG7)
Figure 34. Read cycle with one waitstate (configured) and one BRDYN generated waitstate (synchronous sampling).
data1 data2
promio_addr
prom_cen/io_sn
promio_data
promio_oen
data2 lead-out
clk
D1
A1
promio_brdyn
data2
ws
brdyn
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