COBHAM GR740 - Page 295

GR740-UM-DS, Nov 2017, Version 1.7 295 www.cobham.com/gaisler
GR740
19.9.2 Memory configuration register 3 (MCFG3)
MCFG3 contains fields to control and monitor memory EDAC.
19.9.3 Memory configuration register 5 (MCFG5)
MCFG5 contains fields to control lead out cycles for the ROM and IO areas.
Table 366. Memory configuration register 3
31 28 27 26
RESERVED ME RESERVED
r
121110987 0
WB RB R PE TCB
0 0 (btstr) N/R
rw rw rw rw
31 : 28 RESERVED
27 Memory EDAC (ME) - Indicates if memory EDAC is present. (read-only)
26 : 12 RESERVED
11 EDAC diagnostic write bypass (WB) - RESERVED in this device, always write to 0.
10 EDAC diagnostic read bypass (RB) - RESERVED in this device, always write to 0.
9RESERVED
8 PROM EDAC enable (PE) - Enable EDAC checking of the PROM area. At reset, this bit is initial-
ized with the value of GPIO line 14 (see section 3.1)
7 : 0 Test checkbits (TCB) - RESERVED in this device. Always write to 0.
Table 367. Memory configuration register 5
31 30 29 23 22 16
RESERVED IOHWS RESERVED
0x00
rw
15 14 13 7 6 0
RESERVED ROMHWS RESERVED
0x00
rw
31 : 30 RESERVED
29:23
IO lead out (IOHWS) - Lead out cycles added to IO accesses are IOHWS(3:0)*2
IOHWS(6:4)
22 : 14 RESERVED
13:7 ROM lead out (ROMHWS) - Lead out cycles added to ROM accesses are
ROMHWS(3:0)*2
ROMHWS(6:4)
6 : 0 RESERVED