GR740-UM-DS, Nov 2017, Version 1.7 358 www.cobham.com/gaisler
GR740
30.3 Registers
The core is programmed through registers mapped into APB address space.
30.3.1 FTMCTRL enable register
Table 454.0x00 - FTMFUNC - FTMCTRL function enable register
30.3.2 Alternative function enable register
Table 455.0x04 - ALTFUNC - Alternative function enable register
Table 453.General purpose register registers
APB address offset Register
0x00 FTMCTRL function enable
0x04 Alternative function enable
0x08 LVDS and memclk pad enable
0x0C PLL new configuration
0x10 PLL reconfigure command
0x14 PLL current configuration (read-only)
0x18 Drive strength configuration register 1
0x1C Drive strength configuration register 2
0x20 Config lockdown register
0x24 - 0xFF Reserved
31 22 21 0
RESERVED FTMEN
0*
rrw
31: 22 RESERVED
21: 0 Pinmux FTMCTRL function enable (FTMEN) - Bit mask corresponding to table 24, used in con-
junction with Alternative function enable to determine pin function. If set to 1, pin is used as FTMC-
TRL function, if 0 alternate or GPIO function
Reset value determined by bootstrap signal GPIO[15], see section 3.3.
31 22 21 0
RESERVED ALTEN
0 0x3fffff
rrw
31: 22 RESERVED
21: 0 Pinmux alternative function enable (ALTFN) - Bit mask corresponding to table 24, used in conjunc-
tion with FTMCTLR function enable register to determine pin function. If set to 1, pin is used as
FTMCTRL or alternative function, if 0 FTMCTRL or GPIO function