GR740-UM-DS, Nov 2017, Version 1.7 359 www.cobham.com/gaisler
GR740
30.3.3 LVDS and memory clock pad enable register
Table 456.0x08 - LVDSMCLK - LVDS and memory clock pad enable register
30.3.4 PLL new configuration register
Table 457.0x0C - PLLNEWCFG - PLL new configuration register
30.3.5 PLL reconfigure command register
Table 458.0x10 - PLLRECFG - PLL reconfigure command register
31 18 17 16 15 8 7 0
RESERVED S
M
E
M
D
M
E
M
RESERVED SPWOE
0110 0xFF
rrwrwr rw
31: 18 RESERVED
17 Enable single-ended SDRAM clock output (SMEM) - 1=enabled, 0=disabled
16 Enable differential SDRAM clock output (DMEM) - 1=enabled, 0=disabled
15: 8 RESERVED
7: 0 Enable LVDS output drivers for SPW links 7...0 (SPWOE) - 1=enabled, 0=disabled
31 19 28 27 26 18 17 9 8 0
RESERVED SWTAG SPWPLLCFG MEMPLLCFG SYSPLLCFG
0000
rrwrwrwrw
31: 29 RESERVED
28: 27 Software tag (SWTAG) - Not fed to PLL. Can be used freely as tag data.
26: 18 New SPWPLL configuration (SPWPLLCFG) - To be used when reprogramming, see table 32
17: 9 New MEMPLL configuration (MEMPLLCFG) - To be used when reprogramming, see table 31
8: 0 New SYSPLL configuration (SYSPLLCFG) - To be used when reprogramming, see table 30
31 32 0
RESERVED RECONF
00
rrw
31: 3 RESERVED
2: 0 Reconfigure PLL (RECONF) - Write "000" then "111" to initiate reconfiguration
To Next Page
Loading...
Need help?
General
