GR740-UM-DS, Nov 2017, Version 1.7 233 www.cobham.com/gaisler
GR740
The core is capable of driving the PCI INTA signal. The Interrupt Request Level (IRL) vector for pro-
cessor 0 is or:ed into a signal that is sampled and forwarded to the PCI INTA signal. The core has a
mask bit (the “Device INT mask” field in the control register) for each bit in the core’s input vector.
The or:ed IRL vector is connected to the first position in this vector. The core also has a PCI interrupt
force bit in the control register to be able to force assertion of PCI INTA.
When the system error PCI signal (SERR) is asserted the core sets the system error bit in the “core
interrupt status” field in the Status & Capability register. If the system interrupt is enabled the core
will also generate a interrupt on the APB bus.
15.9 Reset
The deassertion of the PCI reset is synchronized to the PCI clock and delayed 3 clock cycles. Reset
for the PCI clock domain is generated from the system’s SYS_RESETN input, as described in section
4.3.
15.10 Registers
The core is configured via registers mapped into APB memory address space.
Table 271.GRPCI2: APB registers
APB address offset Register
0x00 Control register
0x04 Status & Capability
0x08 PCI master prefetch burst limit
0x0C AHB to PCI mapping for PCI IO
0x10 DMA Control & Status
0x14 DMA descriptor base
0x18 DMA channel active (read only)
0x1C RESERVED
0x20 - 0x34 PCI BAR to AHB address mapping (Read only)
0x38 RESERVED
0x3C RESERVED
0x40 - 0x7C AHB master to PCI memory address mapping
0x80 PCI trace buffer: control & status
0x84 PCI trace buffer: counter & mode
0x88 PCI trace buffer: AD pattern
0x8C PCI trace buffer: AD mask
0x90 PCI trace buffer: Ctrl signal pattern
0x94 PCI trace buffer: Ctrl signal mask
0x98 PCI trace buffer: AD state
0x9C PCI trace buffer: Ctrl signal state
0xA0 - 0xFF RESERVED
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