GR740-UM-DS, Nov 2017, Version 1.7 331 www.cobham.com/gaisler
GR740
the Multiple-master error (MME) bit will be asserted in the Event register. If a Multiple-master error
occurs the core will be disabled. Note that the core will react to changes on SPI_SEL even if the core
is operating in loop mode and that the core can be configured to ignore SPI_SEL by setting the IGSEL
field in the Mode register.
24.3 Registers
The core is programmed through registers mapped into APB address space.
Table 419.SPI controller registers
APB address offset Register
0x00 Capability register
0x04-0x1C Reserved
0x20 Mode register
0x24 Event register
0x28 Mask register
0x2C Command register
0x30 Transmit register
0x34 Receive register
0x38 Slave Select register
0x3C Automatic slave select register
0x3F-0xFF Reserved
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